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PRODUCT SPECIFICATION
2.4GHz RF transmitter with NRF24E2 embedded 8051 compatible micro-controller and 9 input, 10 bit ADC
FEATURES
* * * * * * * * * * * * 2.4GHz RF transmitter 8051 compatible micro-controller compatible with nRF24E1 9 input 10 bit ADC 100kSPS Single 1.9V to 3.6V supply Internal voltage regulators 2 A standby with wakeup on timer or external pin Internal VDD monitoring Supplied in 36 pin QFN (6x6mm) package 0.18m CMOS technology Low Bill- of Material Ease of design * * * * * * * * * * * * Wireless gamepads Wireless headsets Wireless keyboards Wireless mouse Wireless toys Intelligent sports equipment Industrial sensors PC peripherals Phone peripherals Tags Alarms Remote control
APPLICATIONS
www..com
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June 2004
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
TABLE OF CONTENT 1 GENERAL DESCRIPTION.....................................................................................4 1.1 Quick Reference Data.........................................................................................4 1.2 Block Diagram....................................................................................................5 1.3 Pin Diagram........................................................................................................6 1.4 Glossary of Terms...............................................................................................8 2 ARCHITECTURAL OVERVIEW............................................................................9 2.1 Microcontroller...................................................................................................9 2.2 PWM...............................................................................................................11 2.3 SPI...................................................................................................................11 2.4 Port Logic ........................................................................................................12 2.5 Power Management..........................................................................................12 2.6 RTC Wakeup Timer, Watchdog and RC Oscillator...........................................12 2.7 XTAL Oscillator...............................................................................................12 2.8 AD Converter...................................................................................................12 2.9 Radio Transmitter .............................................................................................13 3 I/O PORTS ............................................................................................................14 3.1 I/O port behavior during RESET.......................................................................14 3.2 Port 0 (P0) .......................................................................................................14 3.3 Port 1 (P1 or SPI port).....................................................................................16 4 nRF2401 2.4GHz TRANSMITTER SUBSYSTEM ................................................20 4.1 RADIO port (Port 2)........................................................................................20 4.2 Modes of operation ..........................................................................................22 4.3 Device configuration..........................................................................................26 4.4 Data package Description.................................................................................31 4.5 Important RF Timing Data.................................................................................33 5 A/D CONVERTER ................................................................................................37 5.1 A/D converter subsystem block diagram............................................................38 5.2 A/D converter registers.....................................................................................38 5.3 A/D converter usage .........................................................................................40 5.4 A/D Converter timing........................................................................................42 5.5 Analog interface guidelines ................................................................................43 6 PWM .....................................................................................................................44 7 INTERRUPTS........................................................................................................45 7.1 Interrupt SFRs..................................................................................................45 7.2 Interrupt Processing..........................................................................................48 7.3 Interrupt Masking .............................................................................................49 7.4 Interrupt Priorities.............................................................................................49 7.5 Interrupt Sampling.............................................................................................50 7.6 Interrupt Latency..............................................................................................50 7.7 Interrupt Latency from Power Down Mode.......................................................50 7.8 Single-Step Operation.......................................................................................50
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
8
WAKEUP TIMER AND WATCHDOG................................................................51 8.1 Tick calibration.................................................................................................51 8.2 RTC Wakeup timer ..........................................................................................52 8.3 Watchdog.........................................................................................................52 8.4 Reset................................................................................................................54 9 POWER SAVING MODES...................................................................................55 9.1 Idle Mode ........................................................................................................55 9.2 Stop Mode.......................................................................................................56 9.3 Power down mode ...........................................................................................56 10 MICROCONTROLLER.....................................................................................58 10.1 Memory Organization.......................................................................................58 10.2 Program format in external EEPROM................................................................59 10.3 Instruction Set...................................................................................................60 10.4 Instruction Timing..............................................................................................67 10.5 Dual Data Pointers............................................................................................67 10.6 Special Function Registers.................................................................................68 10.7 SFR registers unique to NRF24E2 .....................................................................72 10.8 Timers/Counters ...............................................................................................74 10.9 Serial Interface..................................................................................................82 11 ELECTRICAL SPECIFICATIONS....................................................................92 12 PACKAGE OUTLINE .......................................................................................94 12.1 GREEN PACKAGE OUTLINE ......................................................................94 12.2 PACKAGE OUTLINE, saw type.....................................................................95 13 ABSOLUTE MAXIMUM RATINGS.................................................................96 14 Peripheral RF Information....................................................................................98 14.2 PCB layout and de-coupling guidelines..............................................................99 15 Application example...........................................................................................100 15.1 NRF24E2 with single ended matching network.................................................100 15.2 PCB layout example .......................................................................................102 16 Table of Figures.................................................................................................103 17 Table of Tables..................................................................................................104 18 DEFINITIONS .................................................................................................106
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
1
GENERAL DESCRIPTION
The NRF24E2 is the transmitter part of the nRF2401 2.4GHz radio transceiver plus an embedded 8051 compatible microcontroller plus a 10-bit 9 input 100 kSPS AD converter. The circuit is supplied by only one voltage in range 1.9V to 3.6V. The NRF24E2 supports the proprietary and innovative modes of the nRF2401 such as ShockBurstTM. NRF24E2 is also a subset of the nRF24E1 chip, which means that it contains all functions of nRF24E1 except the radio receive functions, and it also means that it is fully program compatible with nRF24E1.
1.1 Quick Reference Data
Parameter
Minimum supply voltage Temperature range Maximum RF output power Maximum RF burst data rate Supply current for microcontroller @ 16MHz @3V Supply current for ADC @100 kSPS Supply current for RF transmit @ -5dBm output power Supply current in Power Down mode max CPU clock frequency max AD conversion rate ADC Differential nonlinearity (DNL) ADC Integral nonlinearity (INL) ADC Spurious free dynamic range (SFDR) Package
Value
1.9 -40 to +85 0 1000 3 0.9 10.5 2 20 100 0.5 0.75 65 36 pin QFN 6x6
Unit
V C dBm kbps mA mA mA MHz kSPS LSB LSB dB
Table 1-1 : NRF24E2 quick reference data
Type Number
NRF24E2 IC NRF24E2G IC
Description
36 pin QFN 6x6, saw 36 pin QFN 6x6, green package
Version
A A
Table 1-2 : NRF24E2 ordering information
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
1.2 Block Diagram
AREF AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 nAD10100K 10-Bit 100kSPS A/D converter 4k byte RAM 1 512 byte 256 byte ROM RAM
VDD_PA = 1.8V ANT1 ANT2 nRF2401 2.4GHz Radio Tranceiver BIAS VSS_PA = 0V
7-channel interrupt UART0 Timer 0 Timer 1 Timer 2
IREF 22k XC1
CPU
8051 compatible Microcontroller
XTAL oscillator
XC2
DVDD PWM DVDD2 VDD VSS
3
SPI
WATCHDOG
WAKEUP timer
Power mgmt Regulators Reset Port logic Low power RC oscillator P0.3 (DIO5) P0.4 (DIO6) P0.5 (DIO7) P0.6 (DIO8) P0.7 (DIO9)
4
P1.2 (DIN0)
P1.0 (DIO0)
P1.1 (DIO1)
P0.0 (DIO2)
P0.1 (DIO3)
SDO SCK SDI CSN
25320 EEPROM
Figure 1-1 NRF24E2 block diagram plus external components
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P0.2 (DIO4)
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
1.3 Pin Diagram
P1.2 (DIN0 ) 36
AREF
AIN1 35
34
AIN2
AIN4
33
VSS
VDD 32
VSS 31
AIN3 30
29
28
VDD
1
27
IREF
AIN0
2
26
AIN5
nRF24E1
DVDD2 3 25 AIN6
QFN36 6x6
P1.0/T2 (DIO0) 4 24 AIN7
P1.1 (DIO1)
5
23
VSS
P0.0 (DIO2)
6
22
VDD
P0.1/RXD (DIO3)
7
21
VSS_PA
P0.2/TXD (DIO4)
8
20
ANT2
P0.3/INT0_N (DIO5)
9
19
ANT1
10 P0.4/INT1_N (DIO6)
11 P0.5/T0 (DIO7)
12 P0.6/T1 (DIO8)
13 P0.7/PWM (DIO9)
14 DVDD
15 VSS
16 XC2
17 XC1
18 VDD_PA
Pin 1 2 3 4 5 6 7 8
Name VDD AIN0 DVDD2 P1.0/T2 P1.1 P0.0 P0.1/RXD P0.2/TXD
Pin function Power Analog input Regulated power Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O
Description Power Supply (1.9-3.6 V DC) ADC input 0 Digital Power Supply , must be connected to regulator output DVDD Port 1, bit 0 or T2 timer input or SPI clock or DIO0 Port 1, bit 1 or SPI dataout or DIO1 Port 0, bit 0 or EEPROM.CSN or DIO2 Port 0, bit 1 or UART.RXD or DIO3 Port 0, bit 2 or UART.TXD or DIO4
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
P0.3/INT0_N P0.4/INT1_N P0.5/T0 P0.6/T1 P0.7/PWM DVDD VSS XC2 XC1 VDD_PA ANT1 ANT2 VSS_PA VDD VSS AIN7 AIN6 AIN5 IREF AREF AIN4 AIN3 VSS VDD VSS AIN2 AIN1 P1.2
Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Regulator output Power Analog output Analog input Regulator output RF RF Power Power Power Analog input Analog input Analog input Analog input Analog input Analog input Analog input Power Power Power Analog input Analog input Digital input
Port 0, bit 3 or INT0_N interrupt or DIO5 Port 0, bit 4 or INT1_N interrupt or DIO6 Port 0, bit 5 or T0 timer input or DIO7 Port 0, bit 6 or T1 timer input or DIO8 Port 0, bit 7 or PWM output or DIO9 Digital voltage regulator output for de-coupling and feed to DVVD2 Ground (0V) Crystal Pin 2 Crystal Pin 1 DC supply (+1.8V) to RF Power Amplifier (ANT1,ANT2) only Antenna interface 1 Antenna interface 2 Ground (0V) Power Supply (1.9-3.6 V DC) Ground (0V) ADC input 7 ADC input 6 ADC input 5 Connection to external Bias reference resistor ADC reference voltage ADC input 4 ADC input 3 Ground (0V) Power Supply (1.9-3.6 V DC) Ground (0V) ADC input 2 ADC input 1 Port 1, bit 2 or SPI datain or DIN0
Table 1-3 : NRF24E2 pin function
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
1.4 Glossary of Terms
Term
ADC CLK CRC CS CE DR FS GFSK GPIO ISM kSPS MCU OD P0 (or P1) PWM PWR_DWN PWR_UP RTC RX SFR SPI SPS ST_BY TX XTAL
Description
Analog to Digital Converter Clock Cyclic Redundancy Check Chip Select Chip Enable Data Ready Full Scale Gaussian Frequency Shift Keying General Purpose In Out Industrial-Scientific-Medical kilo Samples per Second Microcontroller Unit Overdrive (8051) In / Out Port 0 (or Port 1) Pulse Width Modulation Power Down Power Up Real Time Clock Receive (8051) Special Function Register Serial Peripheral Interface Samples per Second Standby Transmit Crystal (oscillator)
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
2
ARCHITECTURAL OVERVIEW
This section will give a brief overview of each of the blocks in the block diagram in Figure 1-1.
2.1 Microcontroller
The NRF24E2 microcontroller is instruction set compatible with the industry standard 8051. Instruction timing is slightly different from the industry standard, typically each instruction will use from 4 to 20 clock cycles, compared with 12 to 48 for the "standard". The interrupt controller is extended to support 3 additional interrupt sources; ADC, SPI, and wakeup timer. There are also 3 timers which are 8052 compatible, plus some extensions, in the microcontroller core. An 8051 compatible UART that can use timer1 or timer2 for baud rate generation in the traditional asynchronous modes is included. The CPU is equipped with 2 data pointers to facilitate easier moving of data in the XRAM area, which is a common 8051 extension. The microcontroller clock is derived directly from the crystal oscillator. 2.1.1 Memory configuration The microcontroller has a 256 byte data ram (8052 compatible, with the upper half only addressable by register indirect addressing). A small ROM of 512 bytes, contains a bootstrap loader that is executed automatically after power on reset or if initiated by software later. The user program is normally loaded into a 4k byte RAM1 from an external serial EEPROM by the bootstrap loader. The 4k byte RAM may also (partially) be used for data storage in some applications. 2.1.2 Boot EEPROM/FLASH If the mask ROM option is not used, the program code for the device must be loaded from an external non-volatile memory. The default boot loader expects this to be a "generic 25320" EEPROM with SPI interface. These memories are available from several vendors with supply ranges down to 1.8V. The SPI interface uses the pins P1.2/DIN0 (EEPROM SDO), P1.0/DIO0 (EEPROM SCK), P1.1/DIO1 (EEPROM SDI) and P0.0/DIO2 (EEPROM CSN). When the boot is completed, the P1.2/DIN0, P1.0/DIO0 and P1.1/DIO1 pins may be used for other purposes such as other SPI devices or GPIO. 2.1.3 Register map The SFR (Special Function Registers) control several of the features of the NRF24E2. Most of the NRF24E2 SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control features that are not available in the standard 8051.
1
Optionally this 4k block of memory can be configured as 2k mask ROM and 2k RAM or 4 k mask ROM
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
The SFR map is shown in the table below. The registers with grey background are registers with industry standard 8051 behavior. Note that the function of P0 and P1 are somewhat different from the "standard" even if the conventional addresses (0x80 and 0x90) are used
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
X000 F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80
IE RADIO (P2) SCON P1 TCON P0 EIP B EIE ACC EICON PSW T2CON IP
X001
X010
X011
X100
X101
X110
X111
RCAP2L
RCAP2H
TL2 T1_1V2
TH2 T2_1V2 TICK_ DV REGX _CTRL DEV_ OFFSET CK_ CTRL
RSTREAS PWM CON ADCCON SBUF EXIF TMOD SP
SPI _DATA PWM DUTY ADC DATAH MPAGE TL0 DPL
SPI _CTRL REGX _MSB ADC DATAL
SPI CLK REGX _LSB ADC STATIC P0_DIR
TEST_ MODE
P0_ALT TH1 DPH1
P1_DIR CKCON DPS
P1_ALT SPC_FNC PCON
TL1 DPH
TH0 DPL1
Table 2-1 : SFR Register map
2.2 PWM
The NRF24E2 has one programmable PWM output, which is the alternate function of PO.7 at pin DIO9. The resolution of the PWM is software programmable to 6, 7 or 8 bits. The frequency of the PWM signal is programmable via a 6 bit prescaler from the XTAL oscillator. The duty cycle is programmable between 0% and 100% via one 8-bit register.
2.3 SPI
NRF24E2 features a simple single buffered SPI master. The 3 lines of the SPI bus (SDI, SCK and SDO) are multiplexed (by writing to register SPI_CTRL) between the GPIO pins (P1.2/DIN0, P1.0/DIO0 and P1.1/DIO1) and the RF transmitter. The SPI hardware does not generate any chip select signal. The programmer will typically use GPIO bits (from port P0) to act as chip selects for one or more external SPI devices. When the SPI interfaces the RF transmitter, the chip selects are available in an internal GPIO port, P2.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
2.4 Port Logic
The device has 1 general purpose input and 10 general purpose bi-directional pins. These are by default configured as GPIO pins controlled by the ports P0 (DIO2 to DIO9) and P1 (DIO0, DIO1, DIN0) of the microcontroller. Most of the GPIO pins can be used for multiple purposes under program control. The alternate functions include two external interrupts, UART RXD and TXD, a SPI master port, three enable/count signals for the timers and the PWM output.
2.5 Power Management
The NRF24E2 can be set into a low power down mode under program control, and also the ADC and RF subsystems can be turned on or off under program control. The CPU will stop, but all RAM's and registers maintain their values. The low power RC oscillator is running, and so are the watchdog and the RTC wakeup timer (if enabled by software). The current consumption in this mode is typically 2A. The device can exit the power down mode by an external pin (INT0_N or INT1_N) if enabled, by the wakeup timer if enabled or by a watchdog reset.
2.6 RTC Wakeup Timer, Watchdog and RC Oscillator
The NRF24E2 contains a low power RC oscillator which can not be disabled, so it will run continuously as long as VDD = 1.8V. RTC Wakeup Timer and Watchdog are two 16 bit programmable timers that run on the RC oscillator LP_OSC clock. The resolution of the watchdog and wakeup timer is programmable from approximately 300s to approximately 80ms. By default the resolution is 10ms. The wakeup timer can be started and stopped by user software. The watchdog is disabled after a reset, but if activated it can not be disabled again, except by another reset
2.7 XTAL Oscillator
Both the microcontroller, ADC and RF front end run on a crystal oscillator generated clock. A range of crystals frequencies from 4 to 20 MHz may be utilised, but 16 MHz is recommended since it gives best over all performance. For details, please see Crystal Specification on page 98. The oscillator may be started and stopped as requested by software.
2.8 AD Converter
The NRF24E2 AD converter has 10 bit dynamic range and linearity with a conversion time of 48 CPU instruction cycles per 10-bit result. The reference for the AD converter is software selectable between the AREF input and an internal 1.22V bandgap reference.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
The converter has 9 inputs selectable by software. Selecting one of the inputs 0 to 7 will convert the voltage on the respective AIN0 to AIN7 pin. Input 8 enables software to monitor the NRF24E2 supply voltage by converting an internal input that is VDD/3 with the 1.22V internal reference selected. The AD converter is typically used in a start/stop mode. The sampling time is then under software control. The converter is by default configured as 10 bits. For special requirements, the AD converter can be configured by software to perform 6, 8 or 12 bit conversions. The converter may also be used in differential mode with AIN0 used as inverting input and one of the other 7 external inputs used as noninverting input. In that case the conversion time can be reduced to approximately 2 s.
2.9 Radio Transmitter
The transmitter part of the circuit has identical functionality to the transmitter part of the nRF2401 single chip RF transceiver. It is accessed through an internal parallel port and / or an internal SPI. NRF24E2 contains no receiver functions. nRF2401 is a radio transceiver for the world wide 2.4 - 2.5 GHz ISM band. The transmitter consists of a fully integrated frequency synthesizer, a power amplifier and a modulator. Output power and frequency channels and other RF parameters are easily programmable by use of the RADIO register, SFR 0xA0. RF current consumption is only 10.5 mA in TX mode (output power -5dBm). For power saving the transmitter can be turned on / off under software control. Further information about the nRF2401 chip can be found at our website http://www.nordicsemi.no.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
3
I/O PORTS
The NRF24E2 have two IO ports located at the default locations for P0 and P1 in standard 8051, but the ports are fully bi-directional CMOS and the direction of each pin is controlled by a _DIR and an _ALT bit for each bit as shown in the table below. Pin Default function DIN0 P1.2 DIO0 P1.0 DIO1 P1.1 DIO2 P0.02 DIO3 P0.1 DIO4 P0.2 DIO5 P0.3 DIO6 P0.4 DIO7 P0.5 DIO8 P0.6 DIO9 P0.7 Table 3-1 : Port functions Alternate=1 T2 (timer2 input) EEPROM_CSN RXD (UART) TXD (UART) INT0_N (interrupt) INT1_N (interrupt) T0 (timer0 input) T1 (timer1 input) PWM SPI_CTRL=01 SPI_DI SPI_SCK SPI_DO
3.1 I/O port behavior during RESET
During the period the internal reset is active (regardless of whether or not the clock is running), all the port pins are configured as inputs. When program execution starts, the DIO ports are still configured as inputs and the program will need to set the _ALT and/or the _DIR register for the pins that should be used as outputs.
3.2 Port 0 (P0)
P0_ALT and P0_DIR control the P0 port function in that order of priority. If the alternate function for port p0.n is set (by P0_ALT.n = 1) the pin will be input or output as required by the alternate function (UART, external interrupt, timer inputs or PWM output), except that the UART RXD direction will still depend on P0_DIR.1. To use INT0_N or INT1_N, the corresponding alternate function must be activated, P0_ALT.3 / P0_ALT.4 When the P0_ALT.n is not set, bit `n' of the port is a GPIO function with the direction controlled by P0_DIR.n.
2
Reserved for use as EEPROM_CSN, works as GPIO P0.0 independent of the "Alternate setting"
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
P0.0 is always a GPIO. It will be activated by the default boot loader after reset and should be connected to the CSN of the boot flash. Pin 10 P0.0 P0.0 Out (DIO2) P0.1 RXD Out (DIO3) P0.2 TXD Out (DIO4) P0.3 INT0_N In (DIO5) P0.4 INT1_N In (DIO6) P0.5 T0 In (DIO7) P0.6 T1 In (DIO8) P0.7 PWM Out (DIO9) Table 3-2 : Port 0 (P0) functions Data in P0_ALT.n,P0_DIR.n 11 00 P0.0 In P0.0 Out RXD TXD INT0_N INT1_N T0 T1 PWM In Out In In In In Out P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Out Out Out Out Out Out Out
01 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 In In In In In In In In
Port 0 is controlled by SFR-registers 0x80, 0x94 and 0x95 listed in the table below. Addr SFR (hex) 80 94 R/W #bit Init value (hex) FF FF Name Function
Port 0, pins DIO9 to DIO2 Direction for each bit of Port 0 0: Output, 1: Input Direction is overridden if alternate function is selected for a pin. 95 R/W 8 00 P0_ALT Select alternate functions for each pin of P0, if corresponding bit in P0_ALT is set, as listed in Table 3-2 : Port 0 (P0) functions, P0.0 has no alternate function,as it is intended as CS for external boot flash memory. It will function as a GPIO bit regardless of P0_ALT.0 Table 3-3 : Port 0 control and data SFR-registers
R/W R/W
8 8
P0 P0_DIR
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
3.3 Port 1 (P1 or SPI port)
The P1 port consists of only 3 pins, one of which is an hardwired input. The function is controlled by SPI_CTRL. When SPI_CTRL is 01, the port is used as a SPI master port. The GPIO bits in port P0 may be used as chip select(s). For timing diagram, please see Figure 3-1 : SPI interface timing. When not used as SPI port, P0_ALT.0 will force P1.0 to be the timer T2 input, P1.1 is now a GPIO. When P0_ALT.0 is 0, also P1.0 is a GPIO. P1.2 (DIN0) is always an input.
Pin
SPI_CTRL = 01
P1_ALT.n = 1 In In3 In
P1.0 SCK Out T2 (DIO0) P1.1 SDO Out P1.1 (DIO1) P1.2 SDI In P1.2 (DIN0) Table 3-4 : Port 1 (P1) functions
SPI_CTRL != 01 P1_ALT.n = 0 P1_DIR.n = 0 P1_DIR.n = 1 P1.0 In P1.0 Out P1.1 P1.2 In In P1.1 P1.2 Out In
Port 1 is controlled by SFR-registers 0x90, 0x96 and 0x97, and only the 3 lower bits of the registers are used. Addr SFR (hex) 90 96 R/W #bit Init value (hex) FF FF Name Function
R/W R/W
3 3
P1 P1_DIR
Port 1, pins DIN0, DIO1 and DIO0 Direction for each bit of Port 1 0: Output, 1: Input Direction is overridden if alternate function is selected for a pin, or if SPI_CTRL=01. bit0, DIN0 is always input.
3
P1.1 is actually under control of P1_DIR.1 even when P1_ALT.1 is 1, since there is no alternate function for this pin.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Select alternate functions for each pin of P1 if corresponding bit in P1_ALT is set, as listed in Table 3-4 : Port 1 (P1) functions If SPI_CTRL is `01', the P1 port is used as SPI master data and clock : 2 -> SDI - input to NRF24E2 from slave 1 -> SDO - output from NRF24E2 to slave 0 -> SCK - output from NRF24E2 to slave Table 3-5 : Port 1 control and data SFR-registers
97
R/W
3
00
P1_ALT
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
P1 may also be configured as a SPI master port , and is then controlled by the 3 SFR registers 0xB2, 0xB3, 0xB4 as shown in the table below. Addr SFR (hex) B2 B3 R/W #bit Init Name (hex ) 0 SPI_DATA 0 SPI_CTRL Function
SPI data input/output 00 -> SPI not used no clock generated 01 -> SPI connected to port P1 (as for booting) another GPIO must be used as chip select (see also Table 3-4 : Port 1 (P1) functions) 10 -> SPI connected to RADIO transmitter for TX or for configuration (see Table 4-2 : RADIO register ) 11 -> reserved, do not use B4 R/W 2 0 SPICLK Divider factor from CPU clock to SPI clock 00: 1/8 of CPU clock frequency 01: 1/16 of CPU clock frequency 10: 1/32 of CPU clock frequency 11: 1/64 of CPU clock frequency The CPU clock is the oscillator generated clock described in Crystal Specification page 98 Table 3-6 : SPI control and data SFR-registers
R/W R/W
8 2
3.3.1 SPI interface operation Whenever SPI_DATA register is written to, a sequence of 8 pulses is started on SCK, and the 8 bits of SPI_DATA register are clocked out on SDO with msb first. Simultaneously 8 bits from SDI are clocked into SPI_DATA register. Ouput data is shifted on negedge SCK, and input data is read on posedge SCK. This is illustrated in Figure 3-1 : SPI interface timing. When the 8 bits are done, SPI_READY interrupt (EXIF.5) goes active, and the 8 bits from SDI may be read from SPI_DATA register. The EXIF.5 bit must be cleared before starting another SPI transaction by writing to SPI_DATA register again. SCK, SDO and SDI may be external pins or internal signals, as defined in SPI_CTRL register.
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NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
End of write to SPI_DATA register
SCK
SDO
MSB
LSB
SDI SPI_READY interrupt tdSCK
MSB
LSB
thSDI tdSDO tsSDI
t cSCK tdready
Figure 3-1 : SPI interface timing tcSCK : SCK cycle time, as defined by SPICLK register. tdSCK : time from writing to SPI_DATA register to first SCK pulse, tdSCK = tcSCK / 2 tdSDO : delay from negedge SCK to new SDO output data, may vary from -40ns to 40ns tsSDI : SDI setup time to posedge SCK, tsSDI > 45ns. thSDI : SDI hold time to posedge SCK, thSDI > 0ns. tdready : time from last SCK pulse to SPI_READY interrupt goes active tdready = 7 CPU clock cycles Note that the above delay, setup and hold time numbers only apply for SPI connected to Port 1; as when SPI is connected to the Radio, SCK,SDO,SDI are all internal signals, not visible to the user. Minimum time between two consecutive SPI transactions will be : 8.5 tcSCK + tdready + tSW where tSW is the time taken by the software to process SPI_READY interrupt, and write to SPI_DATA register.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
4
nRF2401 2.4GHz TRANSMITTER SUBSYSTEM
4.1 RADIO port (Port 2)
The transmitter is controlled by the RADIO port. The RADIO port uses the address normally used by port P2 in standard 8051. However since the radio transmitter is on chip, the port is not bi-directional. The power on default values in the port "latch" also differs from traditional 8051 to match the requirements of the radio transmitter subsystem. Operation of the transmitter is controlled by SFR registers RADIO and SPI_CTRL: Addr SFR (hex) A0 R/W #bit Init value (hex) 80 Name Function
R/W
8
RADIO
General purpose IO for interface to nRF2401 radio transmitter subsystem
00 -> SPI not used 01 -> SPI connected to port P1 (boot) 10 -> SPI connected to nRF2401 TX 11 -> reserved, do not use Table 4-1 : nRF2401 2.4GHz transmitter subsystem control registers - SFR 0xA0 and 0xB3
B3
R/W
2
0
SPI_CTRL
The bits of the RADIO register correspond to similar pins of the nRF2401 single chip, as shown in Table 4-2 : RADIO register . In the documentation the pin names are used, so please note that setting or reading any of these nRF2401 pins, means to write or read the RADIO SFR register accordingly. Please also note that in the transmitter documentation the notation MCU means the onchip 8051 compatible microcontroller. RADIO register bit corresponding pin name on single chip nRF2401 2.4GHz Transceiver Read : This is a write only register, if read, all bits will be undefined Write : 7: PWR_UP, power on radio PWR_UP 6: CE, Activate TX mode CE 5: Not used CLK2 4: Not used 3: CS, Chip select configuration mode CS 2: Not used 1: CLK1, clock for data input CLK1 0: DATA, configuration or TX data input DATA Table 4-2 : RADIO register - SFR 0xA0, default initial data value is 0x80.
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Note : Some of the pins are overridden when SPI_CTRL=1x, see Table 4-3 : Transmitter SPI interface.
4.1.1 Controlling the transmitter via SPI interface. It is more convenient to use the built-in SPI interface to do the most common transmitter operations as RF configuration and ShockBurstTM TX. Please see Table 3-6 : SPI control and data SFR-registers for use of SPI interface. The radio port will be connected in different ways to the SPI hardware when SPI_CTRL is `1x'. When SPI_CTRL is `0x', all radio pins are connected directly to their respective port pins. SPI signal SPI_CTRL=10 (binary) CS RADIO_wr.6 (CE) for ShockBurstTM (active high) RADIO_wr.3 (CS) for Configuration SCK nRF2401/CLK1 SDI not used SDO nRF2401/DATA Table 4-3 : Transmitter SPI interface.
SPI_CTRL RADIO register
read bitno write -------------------------7 PWR_UP DR2 6 CE CLK2 5 CLK2 DOUT2 4 3 CS DR1 2 CLK1 1 CLK1 DATA 0 DATA
2 MUX
nRF2401 Tranceiver
input output -----------------------PWR_UP CE DR2 CLK2 CLK2 DOUT2 CS DR1 CLK1 CLK1 DATA DATA
3
MUX
2
MUX
SPI interface
SDI SCK SDO
MUX
2 3
Figure 4-1 : Transmitter interface
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4.1.2 RADIO port behavior during RESET During the period the internal reset is active (regardless of whether or not the clock is running), the RADIO outputs that control the nRF2401 transmitter subsystem are forced to their respective default values (RADIO.3=0 (CS), RADIO.6=0 (CE) RADIO.7=1 (PWR_UP)). When program execution starts, these ports will remain at those default levels until the programmer actively changes them by writing to the RADIO register.
4.2 Modes of operation
4.2.1 Overview The transmitter subsystem can be set in the following main modes depending on three control pins:
Mode
Active (TX) Configuration Stand by Power down
PWR_UP
1 1 1 0
CE
1 0 0 X
CS
0 1 0 X
Table 4-4 transmitter subsystem main modes
4.2.2
Active modes
The transmitter subsystem has two active (TX) modes: * * ShockBurstTM Direct Mode (not supported by NRF24E2)
The device functionality in these modes is decided by the content of a configuration word. This configuration word is presented in the configuration section. Please note that Direct mode is not supported, as this will require a more powerful CPU than 8051.
4.2.3 ShockBurstTM The ShockBurstTM technology uses on-chip FIFO to clock in data at a low data rate and transmit at a very high rate thus enabling extremely power reduction. When operating the transmitter subsystem in ShockBurstTM, you gain access to the high data rates (1 Mbps) offered by the 2.4 GHz band without the need of a costly, high-speed microcontroller (MCU) for data processing. By putting all high speed signal processing related to RF protocol on-chip, the NRF24E2 offers the following benefits: * Highly reduced current consumption
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* *
Lower system cost (facilitates use of less expensive microcontroller) Greatly reduced risk of `on-air' collisions due to short transmission time
The transmitter subsystem can be programmed using a simple 3-wire interface where the data rate is decided by the speed of the CPU. By allowing the digital part of the application to run at low speed while maximizing the data rate on the RF link, the ShockBurstTM mode reduces the average current consumption in applications considerably. 4.2.3.1 ShockBurstTM principle When the transmitter subsystem is configured in ShockBurstTM, TX operation is conducted in the following way (10 kbps for the example only).
10 kbps effective
8051 MCU
nRF2401 subsyst.
FIFO
ShockBurstTM
1Mbps
Figure 4-2Clocking in data with CPU and sending with ShockBurstTM technology
Without ShockBurstTM, running at speed dictated by 10Kbs MCU
10mA period
10mA period
10Kbs MCU with ShockBurst TM
0
20
40
60
80
100
120
140
160
180
200
220
240
Time mS
Figure 4-3 RF Current consumption with & without ShockBurstTM technology
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nRF2401 in ShockBurst TM TX (CE=hi)? YES
NO
Data content of registers:
uController Loading ADDR and PAYLOAD data ADDR PAYLOAD
Maximum 256 bits
nRF2401 Calculating CRC
ADDR
PAYLOAD
CRC
NO CE=Low?
YES
nRF2401 Adding Preamble
Preamble
ADDR
PAYLOAD
CRC
nRF2401 Sending ShockBurst TM Package (250 or 1000kbps)
Input FIFO not Empty
YES Sending completed?
NO
Figure 4-4 Flow Chart ShockBurstTM Transmit of transmitter subsystem 4.2.3.2 ShockBurstTM Transmit: 4.2.3.2.1 CPU interface pins: CE, CLK1, DATA 1. When the application CPU has data to send, set CE high. This activates nRF2401 on-board data processing. 2. The address of the receiving node (RX address) and payload data is clocked into the transmitter subsystem. The application protocol or CPU sets the speed <1Mbps (ex: 10kbps). 3. CPU sets CE low, this activates a ShockBurstTM transmission. 4. ShockBurstTM: * RF front end is powered up * RF package is completed (preamble added, CRC calculated) * Data is transmitted at high speed (250 kbps or 1 Mbps configured by user).
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*
transmitter subsystem returns to stand by when finished
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4.3 Device configuration
All configuration of the transmitter subsystem is done via a 3-wire interface interface (CS, CLK1 and DATA) to a single configuration register. The configuration word can be up to 18 bits long. The configuration bits (DATA) must be clocked (by CLK1) into transmitter subsystem, with msb first, while CS=1. No more than 18 bits may be downloaded.
4.3.1 Configuration for ShockBurstTM operation The configuration word in ShockBurstTM enables the transmitter subsystem to handle the RF protocol. Once the protocol is completed and loaded into transmitter subsystem only one byte, bit[7:0], needs to be updated during actual operation. The configuration blocks dedicated to ShockBurstTM is as follows: * CRC: Enables on-chip CRC generation and de-coding. NOTE: The CPU must generate an address and a payload section that fits the configuration of the nRF24x1 subsystem that is to receive the data. When using the transmitter subsystem on-chip CRC feature ensures that CRC is enabled and uses the same length for both the TX and RX devices.
PRE-AMBLE ADDRESS PAYLOAD CRC
Figure 4-5Data packet set-up
4.3.2 Configuration for Direct Mode operation For direct mode operation only the two first bytes (bit[15:0]) of the configuring word is relevant.
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4.3.3
Configuration Word overview
Bit Number position of bits Name Function
ShockBurstTM configuration
> 17
reserved
must not be written
17
1
CRC_L
8 or 16 bit CRC
16
1
CRC_EN
Enable on-chip CRC generation.
15
1
reserved, should be zero
CM Communication mode (Direct or ShockBurstTM)
General device configuration
14
1
13
1
RFDR_SB
RF data rate (1Mbps requires 16MHz crystal)
12:10
3
XO_F
Crystal frequency
9:8
2
RF_PWR
RF output power
7:1
7
RF_CH#
Frequency channel
0
1
reserved, must be zero
Table 4-5 Table of configuration words. The configuration word is shifted in MSB first on positive CLK1 edges. New configuration is enabled on the falling edge of CS. Not more than maximum 18 bits must be shifted. NOTE. On the falling edge of CS, the transmitter subsystem updates the number of bits actually shifted in during the last configuration.
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4.3.4 Configuration Word Detailed Description The following describes the function of the 24 bits (bit 23 = MSB) that is used to configure the transmitter subsystem. General Device Configuration: bit[15:0] ShockBurstTM Configuration: bit[17:16]
CRC D17 CRC Mode 1 = 16bit, 0 = 8bit 0 D16 CRC 1 = enable; 0 = disable 1 RF-Programming D10 D9 D8 RF Power 1
Default
LSB
D15 reserved 0
D14 BUF 0
D13 OD 0
D12
D11
D7
D6
D5
D4
D3
D2
D 1 0
D0
reserved
0
XO Frequency 1 1
1
0
0
Channel selection 0 0 0
1
0
Default
Table 4-6 Configuration data word The MSB bit should be loaded first into the configuration register. Default configuration word: h1.0F04.
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4.3.4.1 ShockBurstTM configuration: Bits [17:16] contains the segments of the configuration register dedicated to ShockBurstTM operational protocol. After VDD is turned on ShockBurstTM configuration is done once and remains set whilst VDD is present. During operation only the first byte for frequency channel needs to be changed. 4.3.4.1.1 CRC
CRC_L
17
CRC_E N
16
Table 4-7 CRC setting. Bit 17: CRC_L: CRC length to be calculated in ShockBurstTM. Logic 0: 8 bit CRC Logic 1: 16 bit CRC
Bit: 16: CRC_EN:
Enables on-chip CRC generation.. Logic 0: On-chip CRC generation disabled Logic 1: On-chip CRC generation enabled
NOTE: An 8 bit CRC will increase the number of payload bits possible in each ShockBurstTM data packet, but will also reduce the system integrity. 4.3.4.2 General RF configuration: This section of the configuration word handles RF and device related parameters. 4.3.4.2.1 Modes
reserved
15
CM
14
RFDR_SB
13 12
XO_F
11 10 9
RF_PWR
8
Table 4-8 RF operational settings. Bit 15: Reserved: Bit 14: Communication Mode: Logic 0: transmitter subsystem operates in direct mode. Logic 1: transmitter subsystem operates in ShockBurstTM mode
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Should be set to logic 0.
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Bit 13: RF Data Rate: Logic 0: 250 kbps Logic 1: 1 Mbps NOTE: Utilizing 250 kbps instead of 1Mbps will improve the receiver sensitivity by 10 dB. 1Mbps requires 16MHz crystal. Bit 12-10: XO_F:
Selects the NRF24E2 crystal frequency to be used: XO Frequency Selection
D12
0 0 0 0 1
D11
0 0 1 1 0
D10
0 1 0 1 0
Crystal Frequency [MHz]
4 8 12 16 20
Table 4-9 Crystal frequency setting. Please also see Table 14-2 Crystal specification of the NRF24E2 Bit 9-8: RF_PWR: Sets NRF24E2 RF output power in transmit mode:
RF Output Power D9 D8 P [dBm]
0 0 1 1 0 1 0 1 -20 -10 -5 0
Table 4-10 RF output power setting. 4.3.4.2.2 RF channel
RF_CH#
7 6 5 4 3 2 1
reserved
0
Table 4-11 Frequency channel setting. Bit 7 - 1: RF_CH#: Sets the frequency channel the NRF24E2 operates on. The channel frequency in transmit is given by:
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Channel RF = 2400 MHz + RF _ CH # 1.0 MHz
RF_CH #: between 2400MHz and 2527MHz may be set. Bit 0: Reserved : Must be set to logic 0 (zero).
4.4 Data package Description
PRE-AMBLE ADDRESS PAYLOAD CRC
Figure 4-6 Data Package Diagram The data packet for both ShockBurstTM mode and direct mode communication is divided into 4 sections. These are:
1. PREAMBLE
* * The preamble field is required in ShockBurstTM and Direct modes Preamble is 8 bits in length and is dependent of the first bit of the address. PREAMBLE 1st ADDR-BIT 01010101 0 10101010 1 Preamble is automatically added to the data packet in ShockBurstTM and thereby gives extra space for payload. In Direct mode MCU must handle preamble. The address field is required in ShockBurstTM mode.4 8 to 40 bits length. The data to be transmitted In Shock-Burst mode payload size is 256 bits minus the following: (Address: 8 to 40 bits. + CRC 8 or 16 bits). In Direct mode the maximum packet size (length) is for 1Mbps for 4ms: 4000 bits (4ms). The CRC is optional in ShockBurstTM mode, and is not used in Direct mode. 8 or 16 bits length
*
2 3
ADDRESS PAYLOAD
* * * * *
4
CRC
* *
Table 4-12 Data package description
4
Suggestions for the use of addresses in ShockBurstTM: In general more bits in the address gives less false detection, which in the end may give lower data packet loss. A. The address made by (5, 4, 3, or 2) equal bytes are not recommended because it in general will make the packet-error-rate increase. B. Addresses where the level shift only one time (i.e. 0x000FFFFFFF) could often be detected in noise that may give a false detection, which again may give raised packeterror-rate. C. First byte of address should not start with 0x55.. or 0xAA.. as this may be interpreted as part of preamble, causing address mismatch for the rest of the address
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4.5 Important RF Timing Data
The following timing applies for operation of transmitter subsystem. 4.5.1 nRF2401 subsystem Timing Information
nRF2401 subsystem timing
PWR_DWN e Configuration ST_BY mode PWR_DWNe Active mode (TX) ST_BY e TX ShockBurstTM Minimum delay from CS to data. Minimum delay from CE to data. Delay between edges Setup time Hold time Delay to finish internal GFSK data Minimum input clock high
Max.
3ms 3ms 195s
Min.
Name
Tpd2sby Tpd2a Tsby2txSB Tcs2data Tce2data Td Ts Th Tfd Thmin
5s 5s 50ns 500ns 500ns 1/data rate 500ns
Table 4-13 Operational timing for transmitter subsystem When the transmitter subsystem is in power down it must always settle in stand by for Tpd2sby (3ms) before it can enter configuration or one of the active modes.
PWR_UP CS CE CLK1 DATA
Tpd2sby
Figure 4-7 Timing diagram for power down (or VDD off) to configuration mode for transmitter subsystem.
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PWR_UP CS CE CLK1 DATA
Tpd2a
Figure 4-8 Power down (or VDD off) to active mode Note that the configuration word will be lost when VDD is turned off and that the device then must be configured before going to one of the active modes. If the device is configured one can go directly from power down to the wanted active mode. Note: CE and CS may not be high at the same time. Setting one or the other decides whether configuration or active mode is entered.
4.5.2 Configuration mode timing When one or more of the bits in the configuration word needs to be changed the following timing apply.
t=0
PWR_UP CS CE CLK1 DATA
Td
CS CE CLK1 DATA
Tcs2data Thmin
MSB
Ts
Th
Figure 4-9 Timing diagram for configuration of transmitter subsystem
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If configuration mode is entered from power down, CS can be set high after Tpd2sby as shown in Figure 4-7.
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4.5.3
ShockBurstTM Mode timing
ShockBurstTM TX:
t=0
PWR_UP CS CE CLK1 DATA ANT1/ANT2 Td
Tsby2txSB
.
Toa
CS CE CLK1 DATA
Tce2data Ts Th
THmin
Figure 4-10 Timing of ShockBurstTM in TX The package length and the data rate give the delay Toa (time on air), as shown in the equation. Databits are the total number of bits, including any CRC and preamble bits which may be added.
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5
A/D CONVERTER
The AD converter subsystem has 10 bit dynamic range and linearity when used at the Nyquist rate. With lower signal frequencies and post filtering, up to 12 bits resolution is possible. The reference for the AD converter is selectable between the AREF input and an internal 1.22V bandgap reference. The converter default setting is 10 bits. For special requirements, the AD converter can be configured to perform 6, 8, 10 or 12 bit conversions. The converter may also be used in differential mode with AIN0 used as inverting input and one of the other 7 external inputs used as noninverting input. In differential mode a slightly improvement (e.g. 2dB for a 10 bit conversion) in SNR may be expected. The AD converter is interfaced to the microcontroller via 4 registers. ADCCON (0xA1) contains the most commonly used control functions like channel and reference selection, power on and start stop control. ADCSTATIC (0xA4) contains infrequently used control functions that will normally not be changed by NRF24E2 applications. The high part of the result is available in the ADCDATAH (0xA2) register, whereas the ADCDATAL (0xA3) will hold the low part of the result (if any) and the end of conversion together with overflow status bits. The complete AD subsystem is switched off by clearing bit NPD (ADCCON.5). The AD converter is normally clocked by the CPU clock divided by 32 (125 to 625 kHz), and the ADC will produce 2 bits of result per clock cycle.
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5.1 A/D converter subsystem block diagram
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
2 ADCRES BIAS singleended to diff
ViVi+ 6-12bit DIFFM DATA
8
ADC DATA H
A/D
2bit/clk
12 4 ADCUF/OF/RNG ADC DATA L
Vref EOC
VDD
2R 4 ADCSEL
START
CPU bus
CSTARTN ADCRUN ADCSEL ADC CON
SEQUENCE CONTROL
1R
band gap
1.22V
ANALOG CONTROL
NPD SLEEP BIAS_SEL DIFFM
ADCRES ADC STATIC
AREF XO clock
1/8
EXTREF
1/4
ADCCLK
CLK8
Figure 5-1 : Block diagram of A/D converter
5.2 A/D converter registers
5.2.1 Bit(s) 7 ADCCON register, SFR 0xA1 Name CSTARTN Function Toggle H -> L -> H to start A/D conversion. This bit is internally synchronized to the ADC clock Ignored if ADCRUN is set.. Set to have the A/D converter run continuously CSTARTN is ignored in this case Set to 0 to put A/D converter in power down state Select reference for A/D converter 0: Use internal band gap reference (nominally 1.22V) 1: Use external pin AREF for reference Ignored if ADCSEL=8. Select input AIN0 to AIN7 ADCSEL=8 will select internal VDD/3, and also automatically select internal bandgap reference For n=0..7, ADCSEL=n will select input pin AINn
6 5 4
ADCRUN NPD EXTREF
3-0
ADCSEL
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Table 5-1 : ADCCON register, SFR 0xA1, default initial data value is 0x80. 5.2.2 Bit(s) 7 ADCSTATIC register, SFR 0xA4 Name DIFFM
Function Enable differential measurements, AIN0 must be used as inverting input and one of the other inputs AIN1 to AIN7, as selected by ADCSEL, must be used as noninverting input. 6 SLEEP Set A/D converter in a reduced power mode 5 CLK8 0 : ADCCLK frequency = CPU clock divided by 32 1 : ADCCLK frequency = CPU clock divided by 8 4-2 ADCBIAS Control A/D converter bias current No need to change for NRF24E2 operation 1-0 ADCRES Select A/D converter resolution 00: 6-bit, result in ADCDATAH 5-0 01: 8-bit, result in ADCDATAH 10: 10-bit, result in ADCDATAH,ADCDATAL.7-6 11: 12-bit, result in ADCDATAH,ADCDATAL.7-4 Table 5-2 : ADCSTATIC register, SFR 0xA4, default initial data value is 0x0A.
5.2.3 Bit(s) 7-0
ADCDATAH register, SFR 0xA2 Name ADCDATAH Function Most significant 8 bits of A/D converter result. For 6-bit conversions ADCDATAH.7-6 is `00'
5.2.4 Bit(s) 7-4
ADCDATAL register, SFR 0xA3 Name ADCDATAL
Function Least significant part of A/D converter result when resolution is 12 or 10 bits, leftjustified. For 10-bit conversions ADCDATAH.5-4 is `00' 3 not used 2 ADCUF Underflow in conversion. Data is all 0's 1 ADCOF Overflow in conversion. Data is all 1's 0 ADCRNG Overflow or underflow in conversion (ADCUF | ADCOF) Table 5-3 : ADC data SFR-registers, SFR 0xA2 and 0xA3.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
5.3 A/D converter usage
5.3.1 End of conversion. A signal ADC_EOC is available in the EXIF.4 bit (Interrupt 2 flag) and it is set to 1 by A/D converter when a conversion (single step or continuous mode) is completed, see Table 7-4 : EXIF Register - SFR 0x91. For timing of ADC_EOC, see Figure 5-3 and Figure 5-4
5.3.2 Measurements with external reference When EXTREF (ADCCON.4) is set to 1 and ADCSEL (ADCCON.3-0) selects an input AIN i ( i.e. AIN 0 to AIN 7), the result in ADCDATA is directly proportional to the ratio between the voltage on the selected input, and the voltage on pin AREF. AIN i voltage = AREF voltage * ADCDATA / 2**N Where N is the number of bits set in ADCRES (ADCSTATIC.1-0) and ADCDATA is the resulting bits in ADCDATAH (and ADCDATAL if N > 8). For differential measurements a simular equation apply : (AIN i - AIN 0)voltage = AREF voltage * (ADCDATA -2**(N-1)) / 2**N This mode of operation is normally selected for sources where the voltage is depending on the supply voltage (or another variable voltage), like shown in Figure 5-2 below. The resistor R1 is selected to keep AREF = 1.5V for the maximum VDD voltage.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
SUPPLY
R1
VDD AREF
nRF24E1
R2 R3 AIN0 AIN1
Figure 5-2 Typical use of A/D with 2 ratiometric inputs
5.3.3 Measurements with internal reference When EXTREF (ADCCON.4) is set to 0 and ADCSEL (ADCCON.3-0) selects an input AIN i (i.e. AIN 0 to AIN 7), the result in ADCDATA is directly proportional to the ratio between the voltage on the selected input, and the internal bandgap reference (nominally 1.22V). if single ended input : AINi voltage = 1.22 V * ADCDATA / 2**N if differential input : (AINi - AIN 0) voltage = 1.22 V * (ADCDATA -2**(N-1)) / 2**N Where N is the number of bits set in ADCRES (ADCSTATIC.1-0) and ADCDATA is the result bits in ADCDATAH (and ADCDATAL if N > 8). This mode of operation is normally selected for sources where the voltage is not depending on the supply voltage.
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5.3.4 Supply voltage measurement When ADCSEL (ADCCON.3-0) is set to 8, the ADC will use the internal bandgap reference (nominally 1.22V), and the input is 1/3 of the voltage on the VDD pins. The result in ADCDATA is thus directly proportional to the VDD voltage. VDD voltage = 3.66 V * ADCDATA / 2**N Where N is the number of bits set in ADCRES (ADCSTATIC.1-0) and ADCDATA is the result bits in ADCDATAH (and ADCDATAL if N > 8).
5.4 A/D Converter timing
ADCCLK
CSTARTN input signal sampled tConv ADC_EOC
ADCDATA
any previously converted value is held until new ADC_EOC
Figure 5-3 : Timing diagram single step conversion. ADCRUN=0, and conversion is started at first posedge ADCCLK after CSTARTN has gone high. A pulse is generated on ADC_EOF when the converted value is available on the ADCDATA bus. Conversion time tConv depends on resolution, tConv = N/2 + 3 clock cycles, where N is number of resolution bits. In the figure a 10 bit conversion is shown. Minimum width of a CSTARTN pulse is 1 clock cycle. If a new CSTARTN pulse comes before previous conversion has finished, the previous conversion will be aborted.
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ADCCLK input signal sample n tConv ADC_EOC tCycle ADCDATA sample n-1 sample n n+1 n+2
Figure 5-4 : Timing diagram continuous mode conversion. ADCRUN=1, and CSTARTN is ignored. Cycle time tCycle is the time between each conversion. tCycle = N/2 +1 clock cycles, where N is number of resolution bits. The figure is showing 10 bit conversions.
5.5 Analog interface guidelines
The input impedance of analog inputs should preferably be in range 100-1000 O, and in any case be less than 10 kO. Small capacitors on inputs (e.g. 200pF) are recommended for decoupling, see also Figure 15-1 for application example. If AIN inputs goes beyond the selected reference voltage, the ADC will clip and the result will be the maximum code. Absolute maximum for any AIN voltage is 2.0V.
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6
PWM
The NRF24E2 PWM output is a one-channel PWM with a 2 register interface. The first register, PWMCON, enables PWM function and PWM period length, which is the number of clock cycles for one PWM period, as shown in the table below. The other register, PWMDUTY, controls the duty cycle of the PWM output signal. When this register is written, the PWM signal will change immediately to the new value. This can result in 4 transitions within one PWM period, but the transition period will always have a "DC value" between the "old" sample and the "new" sample. The table shows how PWM frequency (or period length) and PWM duty cycle are controlled by the settings in the two PWM SFR-registers. For a crystal frequency of 16 MHz, PWM frequency range will be about 1-253 kHz. PWMCON[7:6]
00 01
PWM frequency
0 (PWM module inactive)
PWMDUTY (duty cycle)
0
10
11
1 63 (PWMCON [5 : 0] + 1) 1 f XO 127 ( PWMCON [5 : 0] + 1) 1 f XO 255 ( PWMCON [5 : 0] + 1) f XO
PWMDUTY [5 : 0] 63 PWMDUTY [6 : 0] 127 PWMDUTY 255
PWM is controlled by SFR 0xA9 and 0xAA. Addr SFR (hex) A9 R/W #bit Init (hex) 0 Name Function
R/W
8
PWMCON
AA
R/W
8
0
PWMDUTY
PWM control register 7-6: Enable / period length select 00: Disable PWM 01: Period length is 6 bit 10: Period length is 7 bit 11: Period length is 8 bit 5-0: PWM frequency prescale factor (see table above) PWM duty cycle (6 to 8 bits according to period length)
Table 6-1 : PWM control registers - SFR 0xA9 and 0xAA
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
7
INTERRUPTS
NRF24E2 supports the following interrupt sources:
Description External interrupt, active low, configurable as edge-sensitive or levelsensitive, at Port P0.3 TF0 Timer 0 interrupt INT1_N External interrupt, active low, configurable as edge-sensitive or levelsensitive, at Port P0.4 TF1 Timer 1 interrupt TF2 or EXF2 Timer 2 interrupt TI or RI Receive/transmit interrupt from Serial Port int2 Internal ADC_EOC (end of AD conversion) interrupt int3 Internal SPI_READY interrupt int4 not used in NRF24E2 int5 not used in NRF24E2 wdti Internal RTC wakeup timer interrupt Table 7-1 : NRF24E2 interrupt sources Interrupt signal INT0_N
7.1 Interrupt SFRs
The following SFRs are associated with interrupt control: - IE - SFR 0xA8 (Table 7-2) - IP - SFR 0xB8 (Table 7-3) - EXIF - SFR 0x91 (Table 7-4) - EICON - SFR 0xD8 (Table 7-5) - EIE - SFR 0xE8 (Table 7-6) - EIP - SFR 0xF8 (Table 7-7) The IE and IP SFRs provide interrupt enable and priority control for the standard interrupt unit, as with industry standard 8051. The EXIF, EICON, EIE, and EIP registers provide flags, enable control, and priority control for the extended interrupt unit.
Table 7-2 explains the bit functions of the IE register. Bit IE.7 Function EA - Global interrupt enable. Controls masking of all interrupts. EA = 0 disables all interrupts (EA overrides individual interrupt enable bits). When EA = 1, each interrupt is enabled or masked by its individual enable bit. Reserved. Read as 0. ET2 - Enable Timer 2 interrupt. ET2 = 0 disables Timer 2 interrupt (TF2). ET2 = 1 enables interrupts generated by the TF2 or EXF2 flag.
IE.6 IE.5
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IE.4
ES - Enable Serial Port interrupt. ES = 0 disables Serial Port interrupts (TI and RI). ES = 1 enables interrupts generated by the TI or RI flag. IE.3 ET1 - Enable Timer 1 interrupt. ET1 = 0 disables Timer 1 interrupt (TF1). ET1 = 1 enables interrupts generated by the TF1 flag. IE.2 EX1 - Enable external interrupt 1. EX1 = 0 disables external interrupt 1 (INT1_N). EX1 = 1 enables interrupts generated by the INT1_N pin. IE.1 ET0 - Enable Timer 0 interrupt. ET0 = 0 disables Timer 0 interrupt (TF0). ET0 = 1 enables interrupts generated by the TF0 flag. IE.0 EX0 - Enable external interrupt 0. EX0 = 0 disables external interrupt 0 (INT0_N). EX0 = 1 enables interrupts generated by the INT0_N pin. Table 7-2 : IE Register - SFR 0xA8
Table 7-3 explains the bit functions of the IP register. Bit IP.7 IP.6 IP.5 Function Reserved. Read as 1. Reserved. Read as 0. PT2 - Timer 2 interrupt priority control. PT2 = 0 sets Timer 2 interrupt (TF2) to low priority. PT2 = 1 sets Timer 2 interrupt to high priority. IP.4 PS - Serial Port interrupt priority control. PS = 0 sets Serial Port interrupt (TI or RI) to low priority. PS = 1 sets Serial Port interrupt to high priority. IP.3 PT1 - Timer 1 interrupt priority control. PT1 = 0 sets Timer 1 interrupt (TF1) to low priority. PT1 = 1 sets Timer 1 interrupt to high priority. IP.2 PX1 - External interrupt 1 priority control. PX1 = 0 sets external interrupt 1 (INT1_N) to low priority. PT1 = 1 sets external interrupt 1 to high priority. IP.1 PT0 - Timer 0 interrupt priority control. PT0 = 0 sets Timer 0 interrupt (TF0) to low priority. PT0 = 1 sets Timer 0 interrupt to high priority. IP.0 PX0 - External interrupt 0 priority control. PX0 = 0 sets external interrupt 0 (INT0_N) to low priority. PT0 = 1 sets external interrupt 0 to high priority. Table 7-3 : IP Register - SFR 0xB8 Table 7-4 explains the bit functions of the EXIF register. Bit EXIF.7 Function IE5 - Interrupt 5 flag. IE5 = 1 indicates that a rising edge was detected on the RADIO.DR2 signal.(see ch. 5.1.RADIO) IE5 must be cleared by software. Setting IE5 in software generates an interrupt, if enabled. IE4 - Interrupt 4 flag. IE4 = 1 indicates that a rising edge was detected on the RADIO.DR1 signal.(see ch. 5.1.RADIO) IE4 must be cleared by software. Setting IE4 in software generates an interrupt, if enabled.
EXIF.6
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EXIF.5
IE3 - Interrupt 3 flag. IE3 = 1 indicates that the internal SPI module has sent or received 8 bits, and is ready for a new command. IE3 must be cleared by software. Setting IE3 in software generates an interrupt, if enabled. EXIF.4 IE2 - Interrupt 2 flag. IE2 = 1 indicates that a rising edge was detected on the ADC_EOC signal. (see ch.5.3.1 End of conversion.) IE2 must be cleared by software. Setting IE2 in software generates an interrupt, if enabled. EXIF.3 Reserved. Read as 1. EXIF.2-0 Reserved. Read as 0. Table 7-4 : EXIF Register - SFR 0x91 Table 7-5 explains the bit functions of the EICON register. Bit EICON.7 EICON.6 EICON.5 EICON.4 EICON.3 Function Not used. Reserved. Read as 1. Reserved. Read as 0. Reserved. Read as 0. WDTI - RTC wakeup timer interrupt flag. WDTI = 1 indicates a wakeup timer interrupt was detected. WDTI must be cleared by software before exiting the interrupt service routine. Otherwise, the interrupt occurs again. Setting WDTI in software generates a wakeup timer interrupt, if enabled. Reserved. Read as 0.
EICON.20 Table 7-5 : EICON Register - SFR 0xD8
Table 7-6 explains the bit functions of the EIE register. Function Reserved. Read as 1. EWDI - Enable RTC wakeup timer interrupt. EWDI = 0 disables wakeup timer interrupt (wdti). EWDI = 1 enables interrupts generated by wakeup. EIE.3 EX5 - Enable interrupt 5. EX5 = 0 disables interrupt 5 (RADIO.DR2). EX5 = 1 enables interrupts generated by the RADIO.DR2 signal. EIE.2 EX4 - Enable interrupt 4. EX4 = 0 disables interrupt 4 (RADIO.DR1). EX4 = 1 enables interrupts generated by the RADIO.DR1 signal. EIE.1 EX3 - Enable interrupt 3. EX3 = 0 disables interrupt 3 (SPI_READY). EX3 = 1 enables interrupts generated by the SPI_READY signal. EIE.0 EX2 - Enable interrupt 2. EX2 = 0 disables interrupt 2 (ADC_EOC). EX2 = 1 enables interrupts generated by the ADC_EOC signal. Table 7-6 : EIE Register - SFR 0xE8 Bit EIE.7-5 EIE.4
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Table 7-7 explains the bit functions of the EIP register. Bit EIP.7-5 EIP.4 Function Reserved. Read as 1. PWDI - RTC wakeup timer interrupt priority control. WDPI = 0 sets wakeup timer interrupt (wdti) to low priority. PS = 1 sets wakeup timer interrupt to high priority. EIP.3 PX5 - interrupt 5 priority control. PX5 = 0 sets interrupt 5 (RADIO.DR2) to low priority. PX5 = 1 sets interrupt 5 to high priority. EIP.2 PX4 - interrupt 4 priority control. PX4 = 0 sets interrupt 4 (RADIO.DR1) to low priority. PX4 = 1 sets interrupt 4 to high priority. EIP.1 PX3 - interrupt 3 priority control. PX3 = 0 sets interrupt 3 (SPI_READY) to low priority. PX3 = 1 sets interrupt 3 to high priority. EIP.0 PX2 - interrupt 2 priority control. PX2 = 0 sets interrupt 2 (ADC_EOC) to low priority. PX2 = 1 sets interrupt 2 to high priority. Table 7-7 : EIP Register - SFR 0xF8
7.2 Interrupt Processing
When an enabled interrupt occurs, the CPU vectors to the address of the interrupt service routine (ISR) associated with that interrupt, as listed in Table 7-8. The CPU executes the ISR to completion unless another interrupt of higher priority occurs. Each ISR ends with an RETI (return from interrupt) instruction. After executing the RETI, the CPU returns to the next instruction that would have been executed if the interrupt had not occurred.
Interrupt Description Natural Priority (lowest number gives highest priority) 1 2 3 4 5 6 8 9 10 11 12 Interrupt Vector
INT0_N TF0 INT1_N TF1 TI or RI TF2 or EXF2 int2 int3 int4 int5 wdti
External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial Port transmit or receive Timer 2 interrupt ADC_EOC interrupt SPI_READY interrupt not used in NRF24E2 not used in NRF24E2 RTC wakeup timer
0x03 0x0B 0x13 0x1B 0x23 0x2B 0x43 0x4B 0x53 0x5B 0x63
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interrupt Table 7-8 : Interrupt Natural Vectors and Priorities
An ISR can only be interrupted by a higher priority interrupt. That is, an ISR for a low-level interrupt can be interrupted only by a high-level interrupt. The CPU always completes the instruction in progress before servicing an interrupt. If the instruction in progress is RETI, or a write access to any of the IP, IE, EIP, or EIE SFRs, the CPU completes one additional instruction before servicing the interrupt.
7.3 Interrupt Masking
The EA bit in the IE SFR (IE.7) is a global enable for all interrupts. When EA = 1, each interrupt is enabled/masked by its individual enable bit. When EA = 0, all interrupts are masked. Table 7-9 provides a summary of interrupt sources, flags, enables, and priorities.
Interrupt INT0_N TF0 INT1_N TF1 TI or RI TF2 or EXF2 int2 int3 int4 int5 wdti Description External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial Port transmit or receive Timer 2 interrupt Flag TCON.1 TCON.5 TCON.3 TCON.7 SCON.0 (RI), SCON.1 (TI) T2CON.7 (TF2), T2CON.6 (EXF2) EXIF.4 EXIF.5 EXIF.6 EXIF.7 EICON.3 Enable IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 EIE.0 EIE.1 EIE.2 EIE.3 EIE.4 Control IP.0 IP.1 IP.2 IP.3 IP.4 IP.5 EIP.0 EIP.1 EIP.2 EIP.3 EIP.4
ADC_EOC interrupt SPI_READY interrupt not used in NRF24E2 not used in NRF24E2 RTC wakeup timer interrupt Table 7-9 : Interrupt Flags, Enables, and Priority Control
7.4 Interrupt Priorities
There are two stages of interrupt priority assignment: interrupt level and natural priority. The interrupt level (high, or low) takes precedence over natural priority. All interrupts can be assigned either high or low priority. In addition to an assigned priority level (high or low), each interrupt has a natural priority, as listed in Table 7-8. Simultaneous interrupts with the same priority level (for example, both high) are resolved according to their natural priority. For example, if
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INT0_N and int2 are both programmed as high priority, INT0_N takes precedence. Once an interrupt is being serviced, only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced.
7.5 Interrupt Sampling
The internal timers and serial port generate interrupts by setting their respective SFR interrupt flag bits. The CPU samples external interrupts once per instruction cycle, at the rising edge of CPU_clk at the end of cycle C4. The INT0_N and INT1_N signals are both active low and can be programmed through the IT0 and IT1 bits in the TCON SFR to be either edge-sensitive or level-sensitive. For example, when IT0 = 0, INT0_N is level-sensitive and the CPU sets the IE0 flag when the INT0_N pin is sampled low. When IT0 = 1, INT0_N is edge-sensitive and the CPU sets the IE0 flag when the INT0_N pin is sampled high then low on consecutive samples. To ensure that edge-sensitive interrupts are detected, the corresponding ports should be held high for four clock cycles and then low for four clock cycles. Level-sensitive interrupts are not latched and must remain active until serviced.
7.6 Interrupt Latency
Interrupt response time depends on the current state of the CPU. The fastest response time is five instruction cycles: one to detect the interrupt, and four to perform the LCALL to the ISR.The maximum latency (thirteen instruction cycles) occurs when the CPU is currently executing an RETI instruction followed by a MUL or DIV instruction. The thirteen instruction cycles in this case are: one to detect the interrupt, three to complete the RETI, five to execute the DIV or MUL, and four to execute the LCALL to the ISR. For the maximum latency case, the response time is 13 x 4 =52clock cycles.
7.7 Interrupt Latency from Power Down Mode.
NRF24E2 may be set into Power Down Mode by writing 0x2 or 0x3 to SFR 0xB6, register CK_CTRL. The CPU will then perform a controlled shutdown of clock and power regulator. The system can only be restarted from pins INT0_N or INT1_N, or an RTC wakeup or a Watchdog reset. In this case the CPU cannot respond until the clock and power regulator have restarted, which may take 3 to 4 LP_OSC cycles. This delay may vary from 0.6ms to 4 ms depending on processing, temperature and supply voltage. In the same way, the shutdown also takes from 2 to 3 LP_OSC cycles, which will be in the range of 0.4 - 3ms.
7.8 Single-Step Operation
The NRF24E2 interrupt structure provides a way to perform single-step program execution. When exiting an ISR with an RETI instruction, the CPU will always execute at least one instruction of the task program. Therefore, once an ISR is
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entered, it cannot be re-entered until at least one program instruction is executed. To perform single-step execution, program one of the external interrupts (for example, INT0_N) to be level-sensitive and write an ISR for that interrupt that terminates as follows:
JNB TCON.1,$ ; JB TCON.1,$ ; RETI ; wait for high on INT0_N wait for low on INT0_N return for ISR
The CPU enters the ISR when INT0_N goes low, then waits for a pulse on INT0_N. Each time INT0_N is pulsed, the CPU exits the ISR, executes one program instruction, then re-enters the ISR.
8
WAKEUP TIMER AND WATCHDOG
8.1 Tick calibration
The "TICK" is an interval that is nominally 10ms long. This interval is the unit of resolution both for the watchdog and the RTC wakeup timer. The LP_OSC clock source of the "TICK" is very inaccurate, and may vary from 6ms to 30ms depending on processing, temperature and supply voltage. That means that Watchdog and RTC may not be used for any accurate timing functions. The accuracy can be improved by calibrating the TICK value at regular intervals. The register TICK_DV controls how many LP_OSC periods elapse between each TICK. The frequency of the LP_OSC (between 1 kHz and 5 kHz) can be measured by timer2 in capture mode with t2ex enabled (EXEN2=1). The signal connected to t2ex has exactly half the frequency of LP_OSC. The 16-bit difference between two consecutive captures in SFR-registers{RCAP2H,RCAP2L} is proportional to the LP_OSC period. For details about timer2 see ch. 10.8.3 and Figure 10-5 : Timer 2 - Timer/Counter with Capture
TICK is controlled by SFR 0xB5.
Addr SFR B5
R/W #bit R/W 8
Divider that's used in generating TICK from LP_OSC frequency. fTICK = fLP_OSC / (1 + TICK_DV) The default value gives a TICK of 10ms nominal as default. Table 8-1 : TICK control register - SFR 0xB5
Init hex 1D
Name TICK_DV
Function
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8.2 RTC Wakeup timer
The RTC is a simple 16 bit down counter that produces an interrupt and reloads automatically when the count reaches zero. This process is initially disabled, and will be enabled with the first write to the timer latch. Writing the timer latch will always be followed by a reload of the counter. The counter may be disabled again by writing a disable opcode to the control register. Both the latch and the counter value may be read by giving the respective codes in the control register, see description in Table 8-2 This counter is used for a wakeup sometime in the future (a relative time wakeup call). If `N' is written to the counter, the first wakeup will happen from somewhere between `N+1' and `N+2' "TICK" from the completion of the write, thereafter a new wakeup is issued every "N+1" "TICK" until the unit is disabled or another value is written to the latch. The wakeup timer is connected to the WDTI interrupt of the CPU. The programmer may poll the EICON.3 flag or enable the interrupt. If the oscillator is stopped, the wakeup interrupt will restart the oscillator regardless of the state of EIE.4 interrupt enable. The NRF24E2 do not provide any "absolute time functions". Absolute time functions in NRF24E2 can well be handled in software since our RAM is continuously powered even when in sleep mode. There will be an application note with the required code to implement the complete absolute time function using some 100 bytes of code and 12 IRAM locations (with 2 alarms).
8.3 Watchdog
The watchdog is activated upon writing 0x08 to its control register SFR 0xAD. It can not be disabled by any other means than a reset. The watchdog register is loaded by writing a 16bit value to the two 8-bit data registers (SFR 0xAB and 0xAC) and then the writing the correct opcode to the control register. The watchdog will then count down towards 0 and when 0 is reached the complete microcontroller will be reset . To avoid the reset, the software must load new values into the watchdog register sufficiently often.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
8-bit CPU register REGX_CTRL
8-bit CPU register REGX_MSB
8-bit CPU register REGX_LSB
16-BIT BUS
Load
16-BIT REGISTER
Load
16-BIT DOWN COUNTER
Load
Zero
16-BIT DOWN COUNTER
Zero WAKEUP INT
TICK WATCHDOG_RESET
Figure 8-18-2 : RTC and watchdog block diagram RTC and Watchdog are controlled by SFRs 0xAB, 0xAC and 0xAD. These 3 registers REGX_MSB, REGX_LSB and REGX_CTRL are used to interface the blocks running on the slow LP_OSC clock. The 16-bit register {REGX_MSB, REGX_LSB} can be written or read as two bytes from the CPU. Typical sequences are: Write: Wait until not busy. Write REGX_MSB, Write REGX_LSB, Write REGX_CTRL Read: Wait until not busy. Write REGX_CTRL, Wait until not busy. Read REGX_MSB, Read REGX_LSB Note : please also wait until not busy before accessing SFR 0xB6 CK_CTRL (page 56)
Addr SFR (hex) AB AC
R/W # b i t R/W 8 R/W 8
Init (hex)
Name
Function
0 0
REGX_ MSB REGX_ LSB
Most significant part of 16 bit register for interface to Watchdog and RTC Least significant part of 16 bit register for interface to Watchdog and RTC
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Control for 16 bit register for interface to Watchdog and RTC. Bit 4 is only available on read and is used to flag the interface unit as busy. Bits 3:0 is read/write with the encoding: 0 000: Read from WD register (16 bit) 1 000: Write to WD register (16 bit) 0 010: Read from RTC latch register (16 bit) 1 010: Write to RTC latch register (16 bit) 0 011: Read from RTC counter reg. (16 bit) 1 011: Disable RTC counter (no data) Table 8-2 : RTC and Watchdog SFR-registers
AD
R/W
5
0
REGX_ CTRL
8.4 Reset
NRF24E2 can be reset either by the on-chip power-on reset circuitry or by the on-chip watchdog counter. 8.4.1 Power-on Reset The power-on reset circuitry keeps the chip in power-on-reset state until the supply voltage reaches VDDmin. At this point the internal voltage generators and oscillators start up, the SFRs are initialized to their reset values, as listed in Table 10-10, and thereafter the CPU begins program execution at the standard reset vector address 0x0000. The startup time from power-on reset is about 14 LP_OSC cycles, which in total may vary from 3 to 15ms depending on processing, temperature and supply voltage. 8.4.2 Watchdog Reset If the Watchdog reset signal goes active, NRF24E2 enters the same reset sequence as for power-on reset, that is the internal voltage generators and oscillators start up, the SFRs are initialized to their reset values, as listed in Table 10-10, and thereafter the CPU begins program execution at the standard reset vector address 0x0000. (of the existing program, there is no reboot) The startup time from watchdog reset is somewhat shorter, 12 LP_OSC cycles, which in total may vary from 2.5 to 13ms depending on processing, temperature and supply voltage. 8.4.3 Program reset address The program reset address is controlled by the RSTREAS register, SFR 0xB1, see Table 8-3 This register shows which reset source that caused the last reset, and provides a choice of two different program start addresses. The default value is power-on reset, which starts the boot loader, while a watchdog reset does not reboot, but restarts at address 0 of the already loaded program.
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Addr SFR (hex) B1
R/W #bit
Init (hex) 02
Name
Function
R/W
2
RSTREAS
bit 0: Reason for last reset 0: POR 1: Any other reset source Clear this bit in software to force a reboot after jump to zero (boot loader will load code RAM if this bit is 0) bit 1: Use IROM for reset vector 0: Reset vectors to 0x0000. 1: Reset vectors to 0x8000.
Table 8-3 Reset control registe - SFR 0xB1.
9
POWER SAVING MODES
NRF24E2 provides the two industry standard 8051 power saving modes: idle mode and stop mode, but with only minor power saving; therefore also a non standard power-down mode is provided, where both oscillator and internal power regulators are turned off to achieve more power saving. The bits that control entry into idle and stop modes are in the PCON register at SFR address 0x87, listed in Table 9-1. The bits that control entry into power down mode are in the CK_CTRL register at SFR address 0xB6, listed in Table 9-2 Function SMOD - Serial Port baud-rate doubler enable. When SMOD = 1, the baud rate for Serial Port is doubled. PCON.6-4 Reserved. PCON.3 GF1 - General purpose flag 1. Bit-addressable, general purpose flag for software control. PCON.2 GF0 - General purpose flag 0. Bit-addressable, general purpose flag for software control. PCON.1 STOP - Stop mode select. Setting the STOP bit places the NRF24E2 in stop mode. PCON.0 IDLE - Idle mode select. Setting the IDLE bit places the NRF24E2 in idle mode. Table 9-1 : PCON Register - SFR 0x87 Bit PCON.7
9.1 Idle Mode
An instruction that sets the IDLE bit (PCON.0) causes the NRF24E2 to enter idle mode when that instruction completes. In idle mode, CPU processing is suspended and internal registers and memory maintain their current data. However, unlike the standard 8051, the CPU clock is not disabled internally, thus not much power is saved.
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There are two ways to exit idle mode: activate any enabled interrupt or watchdog reset. Activation of any enabled interrupt causes the hardware to clear the IDLE bit and terminate idle mode. The CPU executes the ISR associated with the received interrupt. The RETI instruction at the end of the of ISR returns the CPU to the instruction following the one that put the NRF24E2 into idle mode. A watchdog reset causes the NRF24E2 to exit idle mode, reset internal registers, execute its reset sequence and begin program execution at the standard reset vector address 0x0000.
9.2 Stop Mode
An instruction that sets the STOP bit (PCON.1) causes the NRF24E2 to enter stop mode when that instruction completes. Stop mode is identical to idle mode, except that the only way to exit stop mode is by watchdog reset Since there is little power saving, stop mode is not recommended, as it is more efficient to use power down mode.
9.3 Power down mode
An instruction that sets the STOP_CLOCK bit (SFR 0xB6 CK_CTRL.1) causes the NRF24E2 to enter power down mode when that instruction completes. In power down mode, CPU processing is suspended, while internal registers and memories maintain their current data. The CPU will perform a controlled shutdown of clock and power regulators. But the transmitter subsystem has to be disabled separately by setting RADIO.7=0 before stopping the clock. The system can only be restarted from a low level on pin INT0_N (P0.3) or INT1_N (P0.4) if enabled (by P0_ALT), or an RTC wakeup interrupt or a Watchdog reset. This will cause the hardware to clear the CK_CTRL.1 bit and terminate power down mode. If there is an enabled interrupt associated with the wakeup event, the CPU executes the ISR associated with that interrupt immediately after power and clocks are restored. The RETI instruction at the end of the of ISR returns the CPU to the instruction following the one that put the NRF24E2 into power down mode. A watchdog reset causes the NRF24E2 to exit power down mode, reset internal registers, execute its reset sequence and begin program execution at the standard reset vector address 0x0000. Note : Before accessing the CK_CTRL register, make sure that the busy bit of RTC/Watchdog SFR 0xAD, bit 4 (page 54) is not set Bit CK_CTRL .0 CK_CTRL .1 Function Not used STOP_CLOCK. Setting the STOP_CLOCK bit places the NRF24E2 in power down mode. Table 9-2 : CK_CTRL register - SFR 0xB6
9.3.1
Clarification about wakeup and interrupt from external events
1: Wakeup and interrupt on pins P0.4 and P0.3 are intended to be parallel exclusive functions. 2: Interrupt circuitry is not active during power down and wakeup not active during power up.
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NRF24E2 2.4 GHz Radio Transmitter with Microcontroller 3: however when the NRF24E2 is started by one of these pins, the event will be captured in the interrupt circuitry also and an interrupt MAY be delivered if enabled. A level interrupt will always be delivered (even if pin has returned high). A falling edge interrupt may be delivered.
9.3.2 Startup time from Power down mode. Startup time consists of a number of LP_OSC cycles + a number of XTAL clock cycles. fLP_OSC may vary from 1 to 5.5kHz over voltage and temperature, but can be measured as described on page 51. fXTAL depends on the selected crystal, as described on page 98. Because frequency fXTAL is much higher, startup time is dominated by fLP_OSC. Startup times are summarized in the table below : Reason of startup Startup time in fLP_OSC cycles Startup time in fXTAL cycles Example of total startup time if fLP_OSC =3kHz if fXTAL =16MHz 4.8 ms 4.0 ms 1.2 ms 1.0 ms
24 24 max 52, see ch. 7.6 RTC interrupt 3 max 52 see ch. 7.6 Table 9-3 : Startup times from Power down mode
Power-on reset Watchdog reset External interrupt
14-15 12 3-4
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10 MICROCONTROLLER
The embedded microcontroller is the DW8051 MacroCell from Synopsys which is similar to the Dallas DS80C320 in terms of hardware features and instruction-cycle timing.
10.1 Memory Organization
FFFFh
81FFh Boot loader 8000h IRAM FFh Upper 128 bytes. 0FFFh Program/data memory. Accessible with movc and movx. 0000h Program memory/Data Memory (ERAM) 80h 7Fh Lower 128 bytes. 00h Accessible by direct and indirect addressing. Accessible by indirect addressing only. Accessible by direct addressing only. 80h Special Function Registers SFR FFh
Internal Data Memory
Figure 10-1 : Memory Map and Organization
10.1.1 Program Memory/Data Memory The NRF24E2 has 4KB of program memory available for user programs located at the bottom of the address space as shown in Figure 10-1. This memory also function as a random access memory and can be accessed with the movx and movc instructions. After power on reset the boot loader loads the user program from the external serial EEPROM and stores it from address 0 in this memory. 10.1.1.1 Memory paging A Special function register, MPAGE, at SFR address 0x92 provides memory paging function. During MOVX A, @Ri and MOVX @Ri, A instructions, the contents of the MPAGE register are placed on the upper eight address bits of memory address.
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10.1.2 Internal Data Memory The Internal Data Memory, illustrated in Figure 10-1, consists of: * * * 128 bytes of registers and scratchpad memory accessible through direct or indirect addressing (addresses 0x00-0x7F). 128 bytes of scratchpad memory accessible through indirect addressing (0x80- 0xFF). 128 special function registers (SFRs) accessible through direct addressing.
The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program status word (PSW) select which bank is in use. The next sixteen bytes form a block of bitaddressable memory space at bit addresses 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. The SFRs and the upper 128 bytes of RAM share the same address range (0x80-0xFF). However, the actual address space is separate and is differentiated by the type of addressing. Direct addressing accesses the SFRs, while indirect addressing accesses the upper 128 bytes of RAM. Most SFRs are reserved for specific functions, as described in 10.6Special Function Registers on page 68. SFR addresses ending in 0h or 8h are bit-addressable.
10.2 Program format in external EEPROM
The table below shows the layout of the first few bytes of the EEPROM image. 7 6 5 4 3 2 1 0 Version Reserved SPEED XO_FREQ (now 00) (now 00) 1: Offset to start of user program (N) 2: Number of 256 byte blocks in user program (includes block 0 that is not full) ... Optional User data, not interpreted by boot loader ... ... N: First byte of user program, goes into ERAM at 0x0000 N+1: Second byte of user program, goes into ERAM at 0x0001 ... Table 10-1 : EEPROM layout 0: The contents of the 4 lowest bits in the first byte is used by the boot loader to set the correct SPI frequency. These fields are encoded as shown below: SPEED (bit 3): EEPROM max speed 0 = 1MHz
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1 = 0.5MHz XO_FREQ (bits 2,1 and 0): Crystal oscillator frequency 000 = 4MHz, 001 = 8MHz, 010 = 12MHz, 011 = 16MHz, 100 = 20MHz The program eeprep can be used to add this header to a program file. Command format: eeprep [options] is the output file of an assembler or compiler is a file suitable for programming the EEPROM (above format with no user data). Both files are "Intelhex" format. The options available for eeprep are: -c n Set crystal frequency in MHz. Valid numbers are 4, 8, 12, 16 (default) and 20 -i Ignore checksums -p n Set program memory size (default 4096 bytes) -s Select slow EEPROM clock (500KHz)
10.3 Instruction Set
All NRF24E2 instructions are binary-code-compatible and perform the same functions that they do in the industry standard 8051. The effects of these instructions on bits, flags, and other status functions is identical to the industry-standard 8051. However, the timing of the instructions is different, both in terms of number of clock cycles per instruction cycle and timing within the instruction cycle. The instruction set is fully compatible to the instruction set of nRF24E1. Table 10-3 to Table 10-8 lists the NRF24E2 instruction set and the number of instruction cycles required to complete each instruction. Symbol Function A Accumulator Rn Register R0-R7 direct Internal register address @Ri Internal register pointed to by R0 or R1 (except MOVX) rel Two's complement offset byte bit Direct bit address #data 8-bit constant #data 16 16-bit constant addr 16 16-bit destination address addr 11 11-bit destination address Table 10-2 : Legend for Instruction Set Table
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Table 10-3 to Table 10-8 define the symbols and mnemonics used in Table 10-2.
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Mnemonic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri
Arithmetic Instructions Description Byte
Add register to A 1 Add direct byte to A 2 Add data memory to A 1 Add immediate to A 2 Add register to A with carry 1 Add direct byte to A with carry 2 Add data memory to A with 1 carry ADDC A, #data Add immediate to A with carry 2 2 SUBB A, Rn Subtract register from A with 1 1 borrow SUBB A, direct Subtract direct byte from A 2 2 with borrow SUBB A, @Ri Subtract data memory from A 1 1 with borrow SUBB A, #data Subtract immediate from A with 2 2 borrow INC A Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC @Ri Increment data memory 1 1 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC @Ri Decrement data memory 1 1 INC DPTR Increment data pointer 1 3 MUL AB Multiply A by B 1 5 DIV AB Divide A by B 1 5 DA A Decimal adjust A 1 1 All mnemonics are copyright (c) Intel Corporation 1980. Table 10-3 : NRF24E2 Instruction Set, Arithmetic Instructions.
Instr. Cycles 1 2 1 2 1 2 1
Hex Code 28-2F 25 26-27 24 38-3F 35 36-37 34 98-9F 95 96-97 94 04 08-0F 05 06-07 14 18-1F 15 16-17 A3 A4 84 D4
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Mnemonic ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri
Logical Instructions Description Byte
AND register to A 1 AND direct byte to A 2 AND data memory to A 1 AND immediate to A 2 AND A to direct byte 2 AND immediate data to direct 3 byte OR register to A 1 1 OR direct byte to A 2 2 OR data memory to A 1 1 OR immediate to A 2 2 OR A to direct byte 2 2 OR immediate data to direct 3 3 byte Exclusive-OR register to A 1 1 Exclusive-OR direct byte to A 2 2 Exclusive-OR data memory to 1 1 A XRL A, #data Exclusive-OR immediate to A 2 2 XRL direct, A Exclusive-OR A to direct byte 2 2 XRL direct, Exclusive-OR immediate to 3 3 #data direct byte CLR A Clear A 1 1 CPL A Complement A 1 1 SWAP A Swap nibbles of A 1 1 RL A Rotate A left 1 1 RLC A Rotate A left through carry 1 1 RR A Rotate A right 1 1 RRC A Rotate A right through carry 1 1 All mnemonics are copyright (c) Intel Corporation 1980. Table 10-4 : NRF24E2 Instruction Set, Logical Instructions.
Instr. Cycles 1 2 1 2 2 3
Hex Code 58-5F 55 56-57 54 52 53 48-4F 45 46-47 44 42 43 68-6F 65 66-67 64 62 63 E4 F4 C4 23 33 03 13
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Instr. Cycles CLR C Clear carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 2 ANL C, bit AND direct bit to carry 2 2 ANL C, /bit AND direct bit inverse to carry 2 2 ORL C, bit OR direct bit to carry 2 2 ORL C, /bit OR direct bit inverse to carry 2 2 MOV C, bit Move direct bit to carry 2 2 MOV bit, C Move carry to direct bit 2 2 All mnemonics are copyright (c) Intel Corporation 1980. Table 10-5 : NRF24E2 Instruction Set, Boolean Instructions.
Mnemonic
Boolean Instructions Description Byte
Hex Code C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92
Mnemonic MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri,
Data Transfer Instructions Description Byte Move register to A Move direct byte to A Move data memory to A Move immediate to A Move A to register Move direct byte to register Move immediate to register Move A to direct byte Move register to direct byte Move direct byte to direct byte Move data memory to direct byte Move immediate to direct byte Move A to data memory Move direct byte to data 1 2 1 2 1 2 2 2 2 3 2 3 1 2
Instr. Cycles 1 2 1 2 1 2 2 2 2 3 2 3 1 2
Hex Code E8-EF E5 E6-E7 74 F8-FF A8-AF 78-7F F5 88-8F 85 86-87 75 F6-F7 A6-A7
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direct MOV @Ri, #data MOV DPTR, #data MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri
memory Move immediate to data 2 memory Move immediate to data pointer 3 Move code byte relative DPTR to A Move code byte relative PC to A Move external data (A8) to A Move external data (A16) to A Move A to external data (A8) Move A to external data (A16) 1 1 1 1 1 1
2 3 3 3 2-9* 2-9* 2-9* 2-9*
76-77 90 93 83 E2-E3 E0 F2-F3 F0 C0 D0 C8-CF C5 C6-C7 D6-D7
Push direct byte onto stack 2 2 Pop direct byte from stack 2 2 Exchange A and register 1 1 Exchange A and direct byte 2 2 Exchange A and data memory 1 1 Exchange A and data memory 1 1 nibble All mnemonics are copyright (c) Intel Corporation 1980.
Table 10-6 : NRF24E2 Instruction Set, Data Transfer Instructions. * Number of cycles is 2 + CKCON.2-0. (CKCON.2-0 is the integer value of the 3LSB of SFR 0x8E CKCON). Default is 3 cycles.
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Mnemonic ACALL addr 11 LCALL addr 16 RET RETI AJMP addr 11 LJMP addr 16 SJMP rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #d, rel
Branching Instructions Description Byte Absolute call to subroutine Long call to subroutine Return from subroutine Return from interrupt Absolute jump unconditional Long jump unconditional Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Jump indirect relative DPTR Jump on accumulator = 0 Jump on accumulator /= 0 Compare A, direct JNE relative 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3
Instr. Cycles 3 4 4 4 3 4 3 3 3 4 4 4 3 3 3 4
Hex Code 11-F1 12 22 32 01-E1 02 80 40 50 20 30 10 73 60 70 B5 B4 B8-BF B6-B7 D8-DF D5
Compare A, immediate JNE 3 4 relative CJNE Rn, #d, rel Compare reg, immediate JNE 3 4 relative CJNE @Ri, #d, Compare ind, immediate JNE 3 4 rel relative DJNZ Rn, rel Decrement register, JNZ 2 3 relative DJNZ direct, rel Decrement direct byte, JNZ 3 4 relative All mnemonics are copyright (c) Intel Corporation 1980. Table 10-7 : NRF24E2 Instruction Set, Branching Instructions. Miscellaneous Instructions Description Byte No operation 1
Mnemonic NOP
Instr. Cycles 1
Hex Code 00
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There is an additional reserved opcode (A5) that performs the same function as NOP. All mnemonics are copyright (c) Intel Corporation 1980. Table 10-8 : NRF24E2 Instruction Set, Miscellaneous Instructions.
10.4 Instruction Timing
Instruction cycles in the NRF24E2 are four clock cycles in length, as opposed to twelve clock cycles per instruction cycle in the standard 8051. This translates to a 3X improvement in execution time for most instructions. However, some instructions require a different number of instruction cycles on the NRF24E2 than they do on the standard 8051. In the standard 8051, all instructions except for MUL and DIV take one or two instruction cycles to complete. In the NRF24E2 architecture, instructions can take between one and five instruction cycles to complete. For example, in the standard 8051, the instructions MOVX A, @DPTR and MOV direct, direct each take two instruction cycles (twenty-four clock cycles) to execute. In the NRF24E2 architecture, MOVX A, @DPTR takes two instruction cycles (eight clock cycles) and MOV direct, direct takes three instruction cycles (twelve clock cycles). Both instructions execute faster on the NRF24E2 than they do on the standard 8051, but require different numbers of clock cycles. For timing of real-time events, use the numbers of instruction cycles from Table 10-3 to Table 10-8 to calculate the timing of software loops. The bytes column of these table indicates the number of memory accesses (bytes) needed to execute the instruction. In most cases, the number of bytes is equal to the number of instruction cycles required to complete the instruction. However, as indicated in Table 10-3, there are some instructions (for example, DIV and MUL) that require a greater number of instruction cycles than memory accesses.By default, the NRF24E2 timer/counters run at twelve clock cycles per increment so that timer-based events have the same timing as with the standard 8051. The timers can be configured to run at four clock cycles per increment to take advantage of the higher speed of the NRF24E2.
10.5 Dual Data Pointers
The NRF24E2 employs dual data pointers to accelerate data memory block moves. The standard 8051 data pointer (DPTR) is a 16-bit value used to address external data RAM or peripherals. The NRF24E2 maintains the standard data pointer as DPTR0 at SFR locations 0x82 and 0x83. It is not necessary to modify code to use DPTR0. The NRF24E2 adds a second data pointer (DPTR1) at SFR locations 0x84 and 0x85. The SEL bit in the DPTR Select register, DPS (SFR 0x86), selects the active pointer. When SEL = 0, instructions that use the DPTR will use DPL and DPH. When SEL=1, instructions that use the DPTR will use DPL1 and DPH1. SEL is the bit 0 of SFR location 0x86. No other bits of SFR location 0x86 are used. All DPTR-related instructions use the currently selected data pointer. To switch the active pointer, toggle the SEL bit. The fastest way to do so is to use the increment instruction (INC DPS). This requires only one instruction to switch from a
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source address to a destination address, saving application code from having to save source and destination addresses when doing a block move. Using dual data pointers provides significantly increased efficiency when moving large blocks of data. The SFR locations related to the dual data pointers are: - 0x82 DPL DPTR0 low byte - 0x83 DPH DPTR0 high byte - 0x84 DPL1 DPTR1 low byte - 0x85 DPH1 DPTR1 high byte - 0x86 DPS DPTR Select (LSB)
10.6 Special Function Registers
The Special Function Registers (SFRs) control several of the features of the NRF24E2. Most of the NRF24E2 SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control features that are not available in the standard 8051. Table 10-9 lists the NRF24E2 SFRs and indicates which SFRs are not included in the standard 8051 SFR space. When writing software for the NRF24E2, use equate statements to define the SFRs that are specific to the NRF24E2 and custom peripherals. In Table 10-9, SFR bit positions that contain a 0 or a 1 cannot be written to and, when read, always return the value shown (0 or 1). SFR bit positions that contain "-" are available but not used. Table 10-10 shows the value of each SFR, after power-on reset or a watchdog reset, together with a pointer to a detailled description of each register. Please note that any unused address in the SFR address space is reserved and should not be written to.
Notes to Table 10-9 on next page :
(1) Not part of standard 8051 architecture. (2) Registers unique to NRF24E2 (3) P0 and P1 differ from standard 8051
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Addr 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x94 0x95 0x96 0x97 0x98 0x99 0xA0 0xA1 0xA2 0xA3 0xA4 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6
Register P0(3) SP DPL DPH DPL1(1) DPH1(1) DPS(1) PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON(1) SPC_FNC(1) P1(3) EXIF(1) MPAGE(1) P0_DIR(2) P0_ALT(2) P1_DIR(2) P1_ALT(2) SCON SBUF RADIO(2) ADCCON(2) ADCDATAH(2) ADCDATAL(2) ADCSTATIC(2) IE PWMCON(2) PWMDUTY(2) REGX_MSB(2) REGX_LSB(2) REGX_CTRL(2) RSTREAS(2) SPI_DATA(2) SPI_CTRL(2) SPICLK(2) TICK_DV(2) CK_CTRL(2)
Bit 7
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port 0 Stack pointer Data pointer 0, low byte Data pointer 0, high byte Data pointer 1, low byte Data pointer 1, high byte 0 0 0 0 0 0 0 SEL SMOD 1 1 GF1 GF0 STOP IDLE TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 GATE C/T M1 M0 GATE C/T M1 M0 Timer/counter 0 value, low byte Timer/counter 1 value, low byte Timer/counter 0 value, high byte Timer/counter 1 value, high byte T2M T1M T0M MD2 MD1 MD0 0 0 0 0 0 0 0 WRS Port 1 bit 2:0 IE5 IE4 IE3 IE2 1 0 0 0 program/data memory page address Direction of Port 0 Alternate functions of Port 0 Direction of Port 1 alt.funct.of Port 1 SM0 SM1 SM2 REN TB8 RB8 TI RI Serial port data buffer PWR_UP DR2/CE CLK2 DOUT2 CS DR1 CLK1 DATA CSTRTN ADCRUN NPD EXTREF ADCSEL High bits of ADC result Low bits of ADC result ADCUF ADCOF ADCRNG DIFFM SLEEP CLK8 ADCBIAS ADCRES EA 0 ET2 ES ET1 EX1 ET0 EX0 PWM_LENGTH PWM_PRESCALE PWM_DUTY_CYCLE High byte of Watchdog/RTC register Low byte of Watchdog/RTC register Control of REGX_MSB and REGX_LSB RFLR SPI_DATA input/output bits SPI_CTRL SPICLK TICK_DV CK_CTRL
Bit 6
Bit 5
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NRF24E2 2.4 GHz Radio Transmitter with Microcontroller 0xB8 0xC8 0xCA 0xCB 0xCC 0xCD 0xD0 0xD8 0xE0 0xE8 0xF0 0xF8 0xFE 0xFF IP T2CON RCAP2L RCAP2H TL2 TH2 PSW EICON(1) ACC EIE(1) B EIP(1) HWREV ----1 TF2 0 PT2 PS PT1 PX1 PT0 PX0 CP/RL2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 Timer/counter 2 capture or reload, low byte Timer/counter 2 capture or reload, high byte Timer/counter 2 value, low byte Timer/counter 2 value, high byte AC F0 RS1 RS0 OV F1 P 1 0 0 WDTI 0 0 0 Accumulator register 1 1 EWDI EX5 EX4 EX3 EX2 B-register 1 1 PWDI PX5 PX4 PX3 PX2 Device hardware revision number Reserved, do not use
CY
-
1 1
Table 10-9 : Special Function Registers summary
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NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Register ACC ADCCON ADCDATAH ADCDATAL ADCSTATIC B CK_CTRL CKCON DPH DPH1 DPL DPL1 DPS EICON EIE EIP EXIF HWREV IE IP MPAGE P0 P0_ALT P0_DIR P1 P1_ALT P1_DIR PCON PSW PWMCON PWMDUTY RADIO RCAP2H RCAP2L REGX_CTRL REGX_LSB REGX_MSB RSTREAS SBUF SCON SP SPC_FNC SPI_CTRL SPI_DATA SPICLK T2CON TCON TH0 TH1
Addr 0xE0 0xA1 0xA2 0xA3 0xA4 0xF0 0xB6 0x8E 0x83 0x85 0x82 0x84 0x86 0xD8 0xE8 0xF8 0x91 0xFE 0xA8 0xB8 0x92 0x80 0x95 0x94 0x90 0x97 0x96 0x87 0xD0 0xA9 0xAA 0xA0 0xCB 0xCA 0xAD 0xAC 0xAB 0xB1 0x99 0x98 0x81 0x8F 0xB3 0xB2 0xB4 0xC8 0x88 0x8C 0x8D
Reset value 0x00 0x80 read only read only 0x0A 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x40 0xE0 0xE0 0x08 0x00,read only 0x00 0x80 0x00 0xFF 0x00 0xFF 0xFF 0x00 0xFF 0x30 0x00 0x00 0x00 0x80 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Description Accumulator register Table 5-1, page 39 Table 5-3, page 39 Table 5-3, page 39 Table 5-2, page 39 B-register Table 9-2, page 56 Table 10-15, page 78 ch.10.5, page 67 ch.10.5, page 67 ch.10.5, page 67 ch.10.5, page 67 ch.10.5, page 67 Table 7-5, page 47 Table 7-6, page 47 Table 7-7, page 48 Table 7-4, page 47 hardware revision no Table 7-2, page 46 Table 7-3, page 46 ch.10.1.1.1, page 58 Table 3-3, page 15 Table 3-3, page 15 Table 3-3, page 15 Table 1-1, page 17 Table 3-5, page 17 Table 3-5, page 17 Table 9-1, page 55 Table 10-11, page 72 Table 6-1, page 44 Table 6-1, page 44 Table 4-2, page 20 ch.10.8.3.3, page 80 ch.10.8.3.3, page 80 Table 8-2, page 54 Table 8-2, page 54 Table 8-2, page 54 Table 8-3, page 55 ch.10.9, page 82 Table 10-19, page 83 Stack pointer do not use Table 3-6, page 18 Table 3-6, page 18 Table 3-6, page 18 Table 10-16, page 80 Table 10-14, page 75 ch.10.8, page 74 ch.10.8, page 74
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller TH2 TICK_DV TL0 TL1 TL2 TMOD 0xCD 0xB5 0x8A 0x8B 0xCC 0x89 0x00 0x1D 0x00 0x00 0x00 0x00 ch.10.8, page 74 Table 8-1, page 51 ch.10.8, page 74 ch.10.8, page 74 ch.10.8, page 74 Table 10-13, page 75
Table 10-10 : Special Function Register reset values and description, alphabetically.
Table 10-11 lists the functions of the bits in the PSW register.
Bit PSW.7 PSW.6 Function CY - Carry flag. Set to 1 when last arithmetic operation resulted in a carry (during addition) or borrow (during subtraction); otherwise cleared to 0 by all arithmetic operations. AC - Auxiliary carry flag. Set to 1 when last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction) the high-order nibble; otherwise cleared to 0 by all arithmetic operations. F0 - User flag 0. Bit-addressable, general purpose flag for software control. RS1 - Register bank select bit 1. Used with RS0 to select a register blank in internal RAM. RS0 - Register bank select bit 0, decoded as: RS1 RS0 Bank selected 0 0 Register bank 0, addresses 0x00-0x07 0 1 Register bank 1, addresses 0x08-0x0F 1 0 Register bank 2, addresses 0x10-0x17 1 1 Register bank 3, addresses 0x18-0x1F OV - Overflow flag. Set to 1 when last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide); otherwise cleared to 0 by all arithmetic operations. F1 - User flag 1. Bit-addressable, general purpose flag for software control. P - Parity flag. Set to 1 when modulo-2 sum of 8 bits in accumulator is 1 (odd parity); cleared to 0 on even parity.
PSW.5 PSW.4 PSW.3
PSW.2
PSW.1 PSW.0
Table 10-11 : PSW Register - SFR 0xD0
10.7 SFR registers unique to NRF24E2
The table below lists the SFR registers that are unique to NRF24E2 (not part of standard 8051 register map) The registers P0, P1 and RADIO use the addresses for the ports P0, P1 and P2 in a standard 8051. Whereas the functionality of these ports is similar to that of the corresponding ports in standard 8051, it is not identical.
Addr SFR 80
R/W #bit R/W 8
Init hex FF
Name P0
Function Port 0, pins DIO9 to DIO2
This bit addressable register differs in usage from "standard 8051"
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Addr SFR 90* 94 95 96 97 A0*
R/W #bit R/W R/W R/W R/W R/W R/W 8(3) 8 8 8(3) 8(3) 8
Init hex FF FF 00 FF 00 80
Name P15 P0_DIR P0_ALT P1_DIR P1_ALT RADIO
Function Port 1, pins DIN0, DI1, DI0 Direction of each GPIO bit of port 0 Select alternate functions for each pin of port 0 Direction for each GPIO bit of port 1 Select alternate functions for each pin of port 1 General purpose IO for interface to 2401 radio, for details see ch. 4 nRF2401 2.4GHz TRANSMITTER SUBSYSTEM ADC control register High 8 bits of ADC result Low bits of ADC result (if any) and status Static configuration data for ADC: PWM control register PWM duty cycle High part of 16 bit register for interface to Watchdog and RTC Low part of 16 bit register for interface to Watchdog and RTC Control of interface to Watchdog and RTC. Reset status and control SPI data input/output 00 -> SPI not used 01 -> connect to P1 10 or 11 -> connect to RADIO Divider from CPU clock to SPI clock TICK Divider. Clock control Test mode register. This register must always be 0 in normal mode. Another 3 test mode registers. Initial values must not be changed.
A1 A2 A3 A4 A9 AA AB AC AD B1 B2 B3 B4 B5 B6 B7
R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R
8 8 8 6 8 8 8 8 5 2 8 2 2 8 2 4
80 XX XX 0A 0 0 0 0 0 02 0 0 0 1D 0 0
ADCCON ADCDATAH ADCDATAL ADCSTATIC PWMCON PWMDUTY REGX_MSB REGX_LSB REGX_CTRL RSTREAS SPI_DATA SPI_CTRL SPICLK TICK_DV CK_CTRL TEST_MODE
BC RW 8 # T1_1V2 BD RW 8 # T2_1V2 BE RW 4 # DEV_OFFSET Table 10-12 : SFR registers unique to NRF24E2
5
Only 3 lower bits are meaningful in P1 and corresponding P1_DIR and P1_ALT
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
10.8 Timers/Counters
The NRF24E2 includes three timer/counters (Timer 0, Timer 1 and Timer 2). Each timer/counter can operate as either a timer with a clock rate based on the CPU clock , or as an event counter clocked by the t0 pin (Timer 0), t1 pin (Timer 1), or the t2 pin (Timer 2). These pins are alternate function bits of Port 0 and 1 as this : t0 is P0.5, t1 is P0.6 and t2 is P1.0, for details please see ch. 3 I/O PORTS. Each timer/counter consists of a 16-bit register that is accessible to software as three SFRs: (Table 10-9 : Special Function Registers) - Timer 0 - TL0 and TH0 - Timer 1 - TL1 and TH1 - Timer 2 - TL2 and TH2
10.8.1 Timers 0 and 1 Timers 0 and 1 each operate in four modes, as controlled through the TMOD SFR (Table 10-13) and the TCON SFR (Table 10-14). The four modes are: - 13-bit timer/counter (mode 0) - 16-bit timer/counter (mode 1) - 8-bit counter with auto-reload (mode 2) - Two 8-bit counters (mode 3, Timer 0 only)
Bit TMOD.7
TMOD.6 TMOD.5 TMOD.4
TMOD.3
TMOD.2 TMOD.1 TMOD.0
Function GATE - Timer 1 gate control. When GATE = 1, Timer 1 will clock only when external interrupt INT1_N = 1 and TR1 (TCON.6) = 1. When GATE = 0, Timer 1 will clock only when TR1 = 1, regardless of the state of INT1_N. C/T - Counter/Timer select. When C/T = 0, Timer 1 is clocked by CPU_clk/4 or CPU_clk/12, depending on the state of T1M (CKCON.4). When C/T = 1, Timer 1 is clocked by the t1 pin. M1 - Timer 1 mode select bit 1. M0 - Timer 1 mode select bit 0, decoded as: M1 M0 Mode 00 Mode 0 : 13-bit counter 01 Mode 1 : 16-bit counter 10 Mode 2 : 8-bit counter with auto-reload 11 Mode 3 : Two 8-bit counters GATE - Timer 0 gate control. When GATE = 1, Timer 0 will clock only when external interrupt INT0_N = 1 and TR0 (TCON.4) = 1. When GATE = 0, Timer 0 will clock only when TR0 = 1, regardless of the state of INT0_N. C/T - Counter/Timer select. When C/T = 0, Timer 0 is clocked by CPU_clk/4 or CPU_clk/12, depending on the state of T0M (CKCON.3). When C/T = 1, Timer 0 is clocked by the t0 pin. M1 - Timer 0 mode select bit 1. M0 - Timer 0 mode select bit 0, decoded as: M1 M0 Mode 00 Mode 0 : 13-bit counter 01 Mode 1 : 16-bit counter 10 Mode 2 : 8-bit counter with auto-reload 11 Mode 3 : Two 8-bit counters
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Table 10-13 : TMOD Register - SFR 0x89
Bit TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 Function TF1 - Timer 1 overflow flag. Set to 1 when the Timer 1 count overflows and cleared when the CPU vectors to the interrupt service routine. TR1 - Timer 1 run control. Set to 1 to enable counting on Timer 1. TF0 - Timer 0 overflow flag. Set to 1 when the Timer 0 count overflows and cleared when the CPU vectors to the interrupt service routine. TR0 - Timer 0 run control. Set to 1 to enable counting on Timer 0. IE1 - Interrupt 1 edge detect. If external interrupt 1 is configured to be edge-sensitive (IT1 = 1), IE1 is set by hardware when a negative edge is detected on the INT1_N external interrupt pin and is automatically cleared when the CPU vectors to the corresponding interrupt service routine. In edge-sensitive mode, IE1 can also be cleared by software. If external interrupt 1 is configured to be level-sensitive (IT1 = 0), IE1 is set when the INT1_N pin is low and cleared when the INT1_N pin is high. In level-sensitive mode, software cannot write to IE1. IT1 - Interrupt 1 type select. When IT1 = 1, the NRF24E2 detects external interrupt pin INT1_N on the falling edge (edge-sensitive). When IT1 = 0, the NRF24E2 detects INT1_N as a low level (level-sensitive). IE0 - Interrupt 0 edge detect. If external interrupt 0 is configured to be edge-sensitive (IT0 = 1), IE0 is set by hardware when a negative edge is detected on the INT0_N external interrupt pin and is automatically cleared when the CPU vectors to the corresponding interrupt service routine. In edge-sensitive mode, IE0 can also be cleared by software. If external interrupt 0 is configured to be level-sensitive (IT0 = 0), IE0 is set when the INT0_N pin is low and cleared when the INT0_N pin is high. In level-sensitive mode, software cannot write to IE0. IT0 - Interrupt 0 type select. When IT0 = 1, the NRF24E2 detects external interrupt INT0_N on the falling edge (edge-sensitive). When IT0 = 0, the NRF24E2 detects INT0_N as a low level (level-sensitive).
TCON.2
TCON.1
TCON.0
Table 10-14 : TCON Register - SFR 0x88
10.8.1.1 Mode 0 Mode 0 operation, illustrated in Figure 10-2 : Timer 0/1 - Modes 0 and 1, is the same for Timer 0 and Timer 1. In mode 0, the timer is configured as a 13-bit counter that uses bits 0- 4 of TL0 (or TL1) and all eight bits of TH0 (or TH1). The timer enable bit (TR0/TR1) in the TCON SFR starts the timer. The C/T bit selects the timer/counter clock source, CPU_clk or t0/t1. The timer counts transitions from the selected source as long as the GATE bit is 0, or the GATE bit is 1 and the corresponding interrupt pin (INT0_N or INT1_N) is deasserted. INT0_N and INT1_N are alternate function bits of Port0, please seeTable 3-1 : Port functions. When the 13-bit count increments from 0x1FFF (all ones), the counter rolls over to all zeros, the TF0 (or TF1) bit is set in the TCON SFR, and the t0_out (or t1_out) pin goes high for one clock cycle. The upper three bits of TL0 (or TL1) are indeterminate in mode 0 and must be masked when the software evaluates the register.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
10.8.1.2 Mode 1 Mode 1 operation is the same for Timer 0 and Timer 1. In mode 1, the timer is configured as a 16-bit counter. As illustrated in Figure 10-2 : Timer 0/1 - Modes 0 and 1, all eight bits of the LSB register (TL0 or TL1) are used. The counter rolls over to all zeros when the count increments from 0xFFFF. Otherwise, mode 1 operation is the same as mode 0.
Figure 10-2 : Timer 0/1 - Modes 0 and 1 10.8.1.3 Mode 2 Mode 2 operation is the same for Timer 0 and Timer 1. In mode 2, the timer is configured as an 8-bit counter, with automatic reload of the start value. The LSB register (TL0 or TL1) is the counter, and the MSB register (TH0 or TH1) stores the reload value. As illustrated in Figure 10-3 : Timer 0/1 - Mode 2, mode 2 counter control is the same as for mode 0 and mode 1. However, in mode 2, when TLn increments from 0xFF, the value stored in THn is reloaded into TLn.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Figure 10-3 : Timer 0/1 - Mode 2 10.8.1.4 Mode 3 In mode 3, Timer 0 operates as two 8-bit counters, and Timer 1 stops counting and holds its value. As shown in Figure 10-4 : Timer 0 - Mode 3, TL0 is configured as an 8-bit counter controlled by the normal Timer 0 control bits. TL0 can count either CPU clock cycles (divided by 4 or by 12) or high-to-low transitions on t0, as determined by the C/T bit. The GATE function can be used to give counter enable control to the INT0_N signal.
Figure 10-4 : Timer 0 - Mode 3
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
TH0 functions as an independent 8-bit counter. However, TH0 can count only CPU clock cycles (divided by 4 or by 12). The Timer 1 control and flag bits (TR1 and TF1) are used as the control and flag bits for TH0. When Timer 0 is in mode 3, Timer 1 has limited usage because Timer 0 uses the Timer 1 control bit (TR1) and interrupt flag (TF1). Timer 1 can still be used for baud rate generation and the Timer 1 count values are still available in the TL1 and TH1 registers.Control of Timer 1 when Timer 0 is in mode 3 is through the Timer 1 mode bits. To turn Timer 1 on, set Timer 1 to mode 0, 1, or 2. To turn Timer 1 off, set it to mode 3. The Timer 1 C/T bit and T1M bit are still available to Timer 1. Therefore, Timer 1 can count CPU_clk/4, CPU_clk/12, or high-to-low transitions on the t1 pin. The Timer 1 GATE function is also available when Timer 0 is in mode 3. 10.8.2 Timer Rate Control The default timer clock scheme for the NRF24E2 timers is twelve CPU clock cycles per increment, the same as in the standard 8051. However, in the NRF24E2, the instruction cycle is four clock cycles. Using the default rate (twelve clocks per timer increment) allows existing application code with real-time dependencies, such as baud rate, to operate properly. However, applications that require fast timing can set the timers to increment every four clock cycles by setting bits in the Clock Control register (CKCON) at SFR location 0x8E, described in Table 10-15 : CKCON Register - SFR 0x. The CKCON bits that control the timer clock rates are: CKCON bit Counter/Timer 5 Timer 2 4 Timer 1 3 Timer 0 When a CKCON register bit is set to 1, the associated counter increments at four-clock intervals. When a CKCON bit is cleared, the associated counter increments at twelve-clock intervals. The timer controls are independent of each other. The default setting for all three timers is 0; that is, twelve-clock intervals. These bits have no effect in counter mode.
Bit CKCON.7,6 CKCON.5 Function Reserved T2M - Timer 2 clock select. When T2M = 0, Timer 2 uses CPU_clk/12 (for compatibility with 80C32); when T2M = 1, Timer 2 uses CPU_clk/4. This bit has no effect when Timer 2 is configured for baud rate generation. T1M - Timer 1 clock select. When T1M = 0, Timer 1 uses CPU_clk/12 (for compatibility with 80C32); when T1M = 1, Timer 1 uses CPU_clk/4. T0M - Timer 0 clock select. When T0M = 0, Timer 0 uses CPU_clk/12 (for compatibility with 80C32); when T0M = 1, Timer 0 uses CPU_clk/4. MD2, MD1, MD0 - Control the number of cycles to be used for external MOVX instructions; number of cycles is 2 + { MD2, MD1, MD0}
CKCON.4 CKCON.3 CKCON.2-0
Table 10-15 : CKCON Register - SFR 0x8E, default initial data value is 0x01, i.e. MOVX takes 3 cycles.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
10.8.3 Timer 2 Timer 2 runs only in 16-bit mode and offers several capabilities not available with Timers 0 and 1. The modes available with Timer 2 are: - 16-bit timer/counter - 16-bit timer with capture - 16-bit auto-reload timer/counter - Baud-rate generator The SFRs associated with Timer 2 are: - T2CON - SFR 0xC8; refer to Table 10-16 : T2CON Register - SFR 0x - RCAP2L - SFR 0xCA - Used to capture the TL2 value when Timer 2 is configured for capture mode, or as the LSB of the 16-bit reload value when Timer 2 is configured for auto-reload mode. - RCAP2H - SFR 0xCB - Used to capture the TH2 value when Timer 2 is configured for capture mode, or as the MSB of the 16-bit reload value when Timer 2 is configured for auto-reload mode. - TL2 - SFR 0xCC - Lower eight bits of the 16-bit count. - TH2 - SFR 0xCD - Upper eight bits of the 16-bit count.
Bit T2CON.7 Function TF2 - Timer 2 overflow flag. Hardware will set TF2 when Timer 2 overflows from 0xFFFF. TF2 must be cleared to 0 by the software. TF2 will only be set to a 1 if RCLK and TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled. EXF2 - Timer 2 external flag. Hardware will set EXF2 when a reload or capture is caused by a high-to-low transition on the t2ex pin, and EXEN2 is set. EXF2 must be cleared to 0 by the software. Writing a 1 to EXF2 forces a Timer 2 interrupt if enabled. RCLK - Receive clock flag. Determines whether Timer 1 or Timer 2 is used for Serial port timing of received data in serial mode 1 or 3. RCLK = 1 selects Timer 2 overflow as the receive clock. RCLK = 0 selects Timer 1 overflow as the receive clock. TCLK - Transmit clock flag. Determines whether Timer 1 or Timer 2 is used for Serial port timing of transmit data in serial mode 1 or 3. TCLK =1 selects Timer 2 overflow as the transmit clock. TCLK = 0 selects Timer 1 overflow as the transmit clock. EXEN2 - Timer 2 external enable. EXEN2 = 1 enables capture or reload to occur as a result of a high-to-low transition on t2ex, if Timer 2 is not generating baud rates for the serial port. EXEN2 = 0 causes Timer 2 to ignore all external events at t2ex. TR2 - Timer 2 run control flag. TR2 = 1 starts Timer 2. TR2 = 0 stops Timer 2. C/T2 - Counter/timer select. C/T2 = 0 selects a timer function for Timer 2. C/T2 = 1 selects a counter of falling transitions on the t2 pin. When used as a timer, Timer 2 runs at four clocks per increment or twelve clocks per increment as programmed by CKCON.5, in all modes except baud-rate generator mode. When used in baud-rate generator mode, Timer 2 runs at two clocks per increment, independent of the state of CKCON.5. CP/RL2 - Capture/reload flag. When CP/RL2 = 1, Timer 2 captures occur on high-to-low transitions of t2ex, if EXEN2 = 1. When CP/RL2 = 0, auto-reloads occur when Timer 2 overflows or when high-to-low transitions occur on t2ex, if EXEN2 = 1. If either RCLK or TCLK is set to 1, CP/RL2 will not function, and Timer 2 will operate in auto-reload mode following each overflow.
T2CON.6
T2CON.5
T2CON.4
T2CON.3
T2CON.2 T2CON.1
T2CON.0
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Table 10-16 : T2CON Register - SFR 0xC8
10.8.3.1 Timer 2 Mode Control Table 10-17 summarizes how the SFR bits determine the Timer 2 mode. RCLK TCLK CP/RL2 TR2 Mode 0 0 1 1 16-bit timer/counter with capture 0 0 0 1 16-bit timer/counter with auto-reload 1 X X 1 Baud-rate generator X 1 X 1 Baud-rate generator X X X 0 Off Table 10-17 : Timer 2 Mode Control Summary 10.8.3.2 16-Bit Timer/Counter Mode Figure 10-5 : Timer 2 - Timer/Counter with Capture illustrates how Timer 2 operates in timer/counter mode with the optional capture feature. The C/T2 bit determines whether the 16-bit counter counts clock cycles (divided by 4 or 12), or high-to-low transitions on the t2 pin. The TR2 bit enables the counter. When the count increments from 0xFFFF, the TF2 flag is set, and t2_out goes high for one clock cycle.
Figure 10-5 : Timer 2 - Timer/Counter with Capture 10.8.3.3 16-Bit Timer/Counter Mode with Capture The Timer 2 capture mode, illustrated in Figure 10-5 : Timer 2 - Timer/Counter with Capture, is the same as the 16-bit timer/counter mode, with the addition of the capture registers and control signals. The CP/RL2 bit in the T2CON SFR enables the capture feature. When CP/RL2 = 1, a high-to-low transition on t2ex when EXEN2 = 1 causes the Timer 2 value to be loaded into the capture registers (RCAP2L and RCAP2H).
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
10.8.3.4 16-Bit Timer/Counter Mode with Auto-Reload When CP/RL2 = 0, Timer 2 is configured for the auto-reload mode illustrated in Figure 10-6 : Timer 2 - Timer/Counter with Auto-Reload. Control of counter input is the same as for the other 16-bit counter modes. When the count increments from 0xFFFF, Timer 2 sets the TF2 flag and the starting value is reloaded into TL2 and TH2. The software must preload the starting value into the RCAP2L and RCAP2H registers. When Timer 2 is in auto-reload mode, a reload can be forced by a high-to-low transition on the t2ex pin, if enabled by EXEN2 = 1.
Figure 10-6 : Timer 2 - Timer/Counter with Auto-Reload 10.8.3.5 Baud Rate Generator Mode Setting either RCLK or TCLK to 1 configures Timer 2 to generate baud rates for Serial port in serial mode 1 or 3. In baud-rate generator mode, Timer 2 functions in auto-reload mode. However, instead of setting the TF2 flag, the counter overflow generates a shift clock for the serial port function. As in normal auto-reload mode, the overflow also causes the preloaded start value in the RCAP2L and RCAP2H registers to be reloaded into the TL2 and TH2 registers. When either TCLK = 1 or RCLK = 1, Timer 2 is forced into auto-reload operation, regardless of the state of the CP/RL2 bit. When operating as a baud rate generator, Timer 2 does not set the TF2 bit. In this mode, a Timer 2 interrupt can be generated only by a high-to-low transition on the t2ex pin setting the EXF2 bit, and only if enabled by EXEN2 = 1.The counter time base in baud-rate generator mode is CPU_clk/2. To use an external clock source, set C/T2 to 1 and apply the desired clock source to the t2 pin.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Figure 10-7 : Timer 2 - Baud Rate Generator Mode
10.9 Serial Interface
The NRF24E2 is configured with one serial port, which is identical in operation to the standard 8051 serial port. The two serial port pins rxd and txd are available as alternate functions of P0.1 and P0.2, for details please see ch. 3 I/O PORTS. The serial port can operate in synchronous or asynchronous mode. In synchronous mode, the NRF24E2 generates the serial clock and the serial port operates in half-duplex mode. In asynchronous mode, the serial port operates in full-duplex mode. In all modes, the NRF24E2 buffers receive data in a holding register, enabling the UART to receive an incoming word before the software has read the previous value. The serial port can operate in one of four modes, as outlined in Table 10-18 Mode
0 1 2 3
Sync/As Baud Clock ync
Sync Async Async Async CPU_clk/4 or CPU_clk/12 Timer 1 or Timer 2 CPU_clk/32 or CPU_clk/64 Timer 1 or Timer 2
Data Bits
8 8 9 9
Start/ Stop
None 1 start, 1 stop 1 start, 1 stop 1 start, 1 stop
9th Bit Function
None None 0, 1, parity 0, 1, parity
Table 10-18 : Serial Port Modes The SFRs associated with the serial port are: - SCON - SFR 0x98 - Serial port control (Table 10-19) - SBUF - SFR 0x99 - Serial port buffer
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Bit
SCON.7 SCON.6
Function
SM0 - Serial port mode bit 0. SM1 - Serial port mode bit 1, decoded as: SM0 SM1 Mode 0 0 0 0 1 1 1 0 2 1 1 3 SM2 - Multiprocessor communication enable. In modes 2 and 3, SM2 enables the multiprocessor communication feature. If SM2 = 1 in mode 2 or 3, RI will not be activated if the received 9th bit is 0. If SM2 = 1 in mode 1, RI will be activated only if a valid stop is received. In mode 0, SM2 establishes the baud rate: when SM2 = 0, the baud rate is CPU_clk/12; when SM2 = 1, the baud rate is CPU_clk/4. REN - Receive enable. When REN = 1, reception is enabled. TB8 - Defines the state of the 9th data bit transmitted in modes 2 and 3. RB8 - In modes 2 and 3, RB8 indicates the state of the 9th bit received. In mode 1, RB8 indicates the state of the received stop bit. In mode 0, RB8 is not used. TI - Transmit interrupt flag. Indicates that the transmit data word has been shifted out. In mode 0, TI is set at the end of the 8th data bit. In all other modes, TI is set when the stop bit is placed on the txd pin. TI must be cleared by the software. RI - Receive interrupt flag. Indicates that a serial data word has been received. In mode 0, RI is set at the end of the 8th data bit. In mode 1, RI is set after the last sample of the incoming stop bit, subject to the state of SM2.In modes 2 and 3, RI is set at the end of the last sample of RB8. RI must be cleared by the software.
SCON.5
SCON.4 SCON.3 SCON.2
SCON.1
SCON.0
Table 10-19 : SCON Register - SFR 0x98 10.9.1 Mode 0 Serial mode 0 provides synchronous, half-duplex serial communication. For Serial Port 0, both serial data input and output occur on rxd pin, and txd provides the shift clock for both transmit and receive. The rxd and txd pins are alternate function bits of Port 0, please also see Table 3-2 : Port 0 (P0) functions for port and pin configuration. The lack of open drain ports on NRF24E2 makes it a programmer responsibility to control the direction of the rxd pin. The serial mode 0 baud rate is either CPU_clk/12 or CPU_clk/4, depending on the state of the SM2. When SM2 = 0, the baud rate is CPU_clk/12; when SM2 = 1, the baud rate is CPU_clk/4. Mode 0 operation is identical to the standard 8051. Data transmission begins when an instruction writes to the SBUF SFR. The UART shifts the data out, LSB first, at the selected baud rate, until the 8-bit value has been shifted out. Mode 0 data reception begins when the REN bit is set and the RI bit is cleared in the corresponding SCON SFR. The shift clock is activated and the UART shifts data in on each rising edge of the shift clock until eight bits have been received. One machine cycle
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
after the 8th bit is shifted in, the RI bit is set and reception stops until the software clears the RI bit.
Figure 10-8 : Serial Port Mode 0 receive timing for low-speed (CPU_clk/12) operation.
Figure 10-9 : Serial Port Mode 0 receive timing for high-speed (CPU_clk/4) operation
Figure 10-10 : Serial Port Mode 0 transmit timing for high-speed (CPU_clk/4) operation
Figure 10-11 : Serial Port Mode 0 transmit timing for high-speed (CPU_clk/4) operation 10.9.2 Mode 1 Mode 1 provides standard asynchronous, full-duplex communication, using a total of ten bits: one start bit, eight data bits, and one stop bit. For receive operations, the stop bit is stored in RB8. Data bits are received and transmitted LSB first. 10.9.2.1 Mode 1 Baud Rate The mode 1 baud rate is a function of timer overflow. Serial port can use either Timer 1 or Timer 2 to generate baud rates. Each time the timer increments from its maximum count (0xFF for Timer 1 or 0xFFFF for Timer 2), a clock is sent to the baud-rate circuit. The clock is then divided by 16 to generate the baud rate. When using Timer 1, the SMOD bit selects whether or not to divide the Timer 1 rollover rate by 2. Therefore, when using Timer 1, the baud rate is determinedby the equation:
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NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
2 SMOD x Timer 1 Overflow 32 SMOD is SFR bit PCON.7 Baud Rate = When using Timer 2, the baud rate is determined by the equation: Timer 2 Overflow Baud Rate = 16 To use Timer 1 as the baud-rate generator, it is best to use Timer 1 mode 2 (8-bit counter with auto-reload), although any counter mode can be used. The Timer 1 reload value is stored in the TH1 register, which makes the complete formula for Timer 1: 2 SMOD clk Baud Rate = x 32 4 x (256 - TH1) The 4 in the denominator in the above equation can be obtained by setting the T1M bit in the CKCON SFR. To derive the required TH1 value from a known baud rate (when TM1 = 0), use the equation: TH1 = 256 2 SMOD clk 128 Baud Rate
You can also achieve very low serial port baud rates from Timer 1 by enabling the Timer 1 interrupt, configuring Timer 1 to mode 1, and using the Timer 1 interrupt to initiate a 16-bit software reload. Table Table 10-20 lists sample reload values for a variety of common serial port baud rates. TH1 Value TH1 Value for 16 MHz for 8 MHz CPU clk CPU clk 19.2 Kb/s 1 0 2 0xF3 9.6 Kb/s 1 0 2 0xE6 0xF3 4.8 Kb/s 1 0 2 0XcC 0xE6 2.4 Kb/s 1 0 2 0x98 0xCC 1.2 Kb/s 1 0 2 0x30 0x98 Table 10-20 : Timer 1 Reload Values for Serial Port Mode 1 Baud Rates To use Timer 2 as the baud-rate generator, configure Timer 2 in auto-reload mode and set the TCLK and/or RCLK bits in the T2CON SFR. TCLK selects Timer 2 as the baud-rate generator for the transmitter; RCLK selects Timer 2 as the baud-rate generator for the receiver. The 16-bit reload value for Timer 2 is stored in the RCAP2L and RCA2H SFRs, which makes the equation for the Timer 2 baud rate: Desired Baud Rate SMOD C/T Timer 1 Mode
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Baud Rate =
clk 32 x (65536 - {RCAP2H, RCAP2L})
where RCAP2H,RCAP2L is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned number. The 32 in the denominator is the result of the CPU_clk signal being divided by 2 and the Timer 2 overflow being divided by 16. Setting TCLK or RCLK to 1 automatically causes the CPU_clk signal to be divided by 2, as shown in Figure 10-7 : Timer 2 - Baud Rate Generator Mode, instead of the 4 or 12 determined by the T2M bit in the CKCON SFR. To derive the required RCAP2H and RCAP2L values from a known baud rate, use the equation: clk RCAP2H,RCAP2L = 65536 - 32 x Baud Rate Table Table 10-21 lists sample values of RCAP2L and RCAP2H for a variety of
desired baud rates.
Baud Rate C/ 16 MHz CPU clk T2 RCAP2H RCAP2L 57.6 Kb/s 0 0xFF 0xF7 19.2 Kb/s 0 0xFF 0xE6 9.6 Kb/s 0 0xFF 0xCC 4.8 Kb/s 0 0xFF 0x98 2.4 Kb/s 0 0xFF 0x30 1.2 Kb/s 0 0xFE 0x5F Table 10-21 : Timer 2 Reload Values for Serial Port Mode 1 Baud Rates
When either RCLK or TCLK is set, the TF2 flag will not be set on a Timer 2 rollover, and the t2ex reload trigger is disabled.
10.9.2.2 Mode 1 Transmit
Figure 10-12 illustrates the mode 1 transmit timing. In mode 1, the UART begins transmitting after the first rollover of the divide-by-16 counter after the software writes to the SBUF register. The UART transmits data on the txd pin in the following order: start bit, eight data bits (LSB first), stop bit. The TI bit is set two clock cycles after the stop bit is transmitted.
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Figure 10-12 : Serial port Mode 1 Transmit Timing 10.9.2.3 Mode 1 Receive Figure 18 illustrates the mode 1 receive timing. Reception begins at the falling edge of a start bit received on rxd_in, when enabled by the REN bit. For this purpose, rxd_in is sampled sixteen times per bit for any baud rate. When a falling edge of a start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter rollover to the bit boundaries.
Figure 10-13 : Serial port Mode 1 Receive Timing For noise rejection, the serial port establishes the content of each received bit by a majority decision of three consecutive samples in the middle of each bit time. This is especially true for the start bit. If the falling edge on rxd_in is not verified by a majority decision of three consecutive samples (low), then the serial port stops reception and waits for another falling edge on rxd_in. At the middle of the stop bit time, the serial port checks for the following conditions: - RI = 0 - If SM2 = 1, the state of the stop bit is 1
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(if SM2 = 0, the state of the stop bit does not matter) If the above conditions are met, the serial port then writes the received byte to the SBUF register, loads the stop bit into RB8, and sets the RI bit. If the above conditions are not met, the received data is lost, the SBUF register and RB8 bit are not loaded, and the RI bit is not set. After the middle of the stop bit time, the serial port waits for another high-to-low transition on the rxd_in pin. Mode 1 operation is identical to that of the standard 8051 when Timers 1 and 2 use CPU_clk/12 (the default).
10.9.3 Mode 2
Mode 2 provides asynchronous, full-duplex communication, using a total of eleven bits: - One start bit - Eight data bits - One programmable 9th bit - One stop bit The data bits are transmitted and received LSB first. For transmission, the 9th bit is determined by the value in TB8. To use the 9th bit as a parity bit, move the value of the P bit (SFR PSW.0) to TB8. The mode 2 baud rate is either CPU_clk/32 or CPU_clk/64, as determined by the SMOD bit. The formula for the mode 2 baud rate is:
Baud Rate = 2 SMOD clk 64
Mode 2 operation is identical to the standard 8051. 10.9.3.1 Mode 2 Transmit
Figure 10-14 illustrates the mode 2 transmit timing. Transmission begins after the first rollover of the divide-by-16 counter following a software write to SBUF . The UART shifts data out on the txd pin in the following order: start bit, data bits (LSB first), 9th bit, stop bit. The TI bit is set when the stop bit is placed on the txd pin.
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NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Figure 10-14 : Serial port Mode 2 Transmit Timing 10.9.3.2 Mode 2 Receive
Figure 10-15 illustrates the mode 2 receive timing. Reception begins at the falling edge of a start bit received on rxd_in, when enabled by the REN bit. For this purpose, rxd_in is sampled sixteen times per bit for any baud rate.When a falling edge of a start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter rollover to the bit boundaries.
Figure 10-15 : Serial port Mode 2 Receive Timing For noise rejection, the serial port establishes the content of each received bit by a majority decision of three consecutive samples in the middle of each bit time. This is especially true for the start bit. If the falling edge on rxd_in is not verified by a majority decision of three consecutive samples (low), then the serial port stops reception and waits for another falling edge on rxd_in. At the middle of the stop bit time, the serial port checks for the following conditions: - RI = 0
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- If SM2 = 1, the state of the stop bit is 1 (if SM2 = 0, the state of the stop bit does not matter) If the above conditions are met, the serial port then writes the received byte to the SBUF register, loads the 9th received bit into RB8, and sets the RI bit. If the above conditions are not met, the received data is lost, the SBUF register and RB8 bit are not loaded, and the RI bit is not set. After the middle of the stop bit time, the serial port waits for another high-to-low transition on the rxd_in.
10.9.4 Mode 3 Mode 3 provides asynchronous, full-duplex communication, using a total of eleven bits: - One start bit - Eight data bits - One programmable 9th bit - One stop bit; the data bits are transmitted and received LSB first The mode 3 transmit and receive operations are identical to mode 2. The mode 3 baud rate generation is identical to mode 1. That is, mode 3 is a combination of mode 2 protocol and mode 1 baud rate. Figure 10-16 illustrates the mode 3 transmit timing. Mode 3 operation is identical to that of the standard 8051 when Timers 1 and 2 use CPU_clk/12 (the default).
Figure 10-16 : Serial port Mode 3 Transmit Timing
Figure 10-17 illustrates the mode 3 receive timing.
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Figure 10-17 : Serial port Mode 3 Receive Timing 10.9.5 Multiprocessor Communications The multiprocessor communication feature is enabled in modes 2 and 3 when the SM2 bit is set in the SCON SFR for a serial port. In multiprocessor communication mode, the 9th bit received is stored in RB8 and, after the stop bit is received, the serial port interrupt is activated only if RB8 = 1. A typical use for the multiprocessor communication feature is when a master wants to send a block of data to one of several slaves. The master first transmits an address byte that identifies the target slave. When transmitting an address byte, the master sets the 9th bit to 1; for data bytes, the 9th bit is 0. When SM2 = 1, no slave will be interrupted by a data byte. However, an address byte interrupts all slaves so that each slave can examine the received address byte to determine whether that slave is being addressed. Address decoding must be done by software during the interrupt service routine. The addressed slave clears its SM2 bit and prepares to receive the data bytes. The slaves that are not being addressed leave the SM2 bit set and ignore the incoming data bytes.
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11 ELECTRICAL SPECIFICATIONS
Conditions: VDD = +3V, VSS = 0V, TA = - 40C to + 85C Symbol Parameter (condition) Notes Min. Operating conditions
VDD TEMP VIH VIL Ci IiL VOH VOL fXTAL fLP_OSC IVDD_MCU IVDD_pwd fOP f RGFSK FCHANNEL PRF PRFC PRFCR PBW PRF2 PRF3 IVDD_TX0 IVDD_TX20 DNL INL SNR VOS G SNR SFDR VBG VFS FS6 Supply voltage Operating Temperature 1.9 -40 VDD- 0.3 VSS 0.55 0.08 VDD- 0.3 VSS 2) I 4 1 3 2 1) 2400 156 >0 1 0 20 +4 3 1000 -20 -40 13 9 I I V I I V V I V I IV 0.5 0.75 59 1 1 58 65 1.22 100 1000 2524 VDD 0.3 20 5.5
Typ.
3.0 +27
Max.
3.6 +85 VDD 0.3
Units
V C V V pF nA V V MHz KHz mA A MHz kHz kbps MHz dBm dB dB kHz dBm dBm mA mA LSB LSB dBFS %FS %FS dBFS
Digital input pin
HIGH level input voltage LOW level input voltage input capacitance input leakage current
Digital output pin
HIGH level output voltage (IOH=0.5mA) LOW level output voltage (IOL=-0.5mA)
Microcontroller
Crystal frequency Low power RC oscillator frequency Supply current @16MHz @3V Average Supply current in power down
General RF conditions
Operating frequency Frequency deviation Data rate ShockBurstTM Channel spacing
Transmitter operation
Maximum Output Power 4) RF Power Control Range RF Power Control Range Resolution 20dB Bandwidth for Modulated Carrier 2nd Adjacent Channel Transmit Power 2MHz 3rd Adjacent Channel Transmit Power 3MHz Supply current @ 0dBm output power 5) Supply current @ -20dBm output power 5) 16
ADC operation
Differential Nonlinearity fIN = 0.9991 kHz Integral Nonlinearity fIN = 0.9991 kHz Signal to Noise Ratio (DC input) Midscale offset Gain Error Signal to Noise Ratio (without harmonics) fIN = 10 kHz Spurious Free Dynamic Range fIN = 10 kHz Internal reference Internal reference voltage drift Reference voltage input (external ref) 6 bit conversion
53
1.1 0.8 fXTAL / 160
dB 1.3 V ppm/C 1.5 V fXTAL / 128 SPS
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NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
FS8 FS10 FS12 IADC t NPD 8 bit conversion 10 bit conversion 12 bit conversion Supply current ADC operation Start-up time from ADC Power down IV IV IV I I fXTAL / 192 fXTAL / 224 fXTAL / 256 1 15 fXTAL / 160 fXTAL / 192 fXTAL / 224 SPS SPS SPS mA s
NOTES: 1) Usable band is determined by local regulations 2) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz) which are specified in the nRF2401 configuration word, please seeTable 14-2 Crystal specification of the NRF24E2. 16MHz is required for 1Mbps operation. 3) Antenna load impedance = 100+j175 4) Current for transmitter RF subsystem only. Antenna load impedance = 100+j175. Effective data rate 250kbps or 1Mbps. I ) Test Level I: 100% production tested at +25C II ) Test Level II: 100% production tested at +25C and sample tested at specified temperatures III ) Test Level III: Sample tested only IV ) Test Level IV: Parameter is guaranteed by design and characterization testing V ) Test Level V: Parameter is typical value only VI) Test Level VI: 100% production tested at +25C. Guaranteed by design and characterization testing for industrial temperature range
Table 11-1 : NRF24E2 Electrical specifications
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12 PACKAGE OUTLINE 12.1 GREEN PACKAGE OUTLINE
NRF24E2G uses the GREEN QFN36 6x6 package, punch type with matt tin plating. Dimensions are in mm.
Package Type
Green QFN36 (6x6 mm) Min typ. Max
A
0.8 0.9
A1
0.0 0.02 0.05
A2
0.65 0.69
b
0.18 0.23 0.3
D/E
D1/E1
e
J
4.47 4.57 4.67
K
4.47 4.57 4.67
L
0.3 0.4 0.5
R
1.735 1.835 1.935
6 BSC
5.75 BSC
0.5 BSC
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Figure 12-1 : NRF24E2G GREEN Package outline.
12.2
PACKAGE OUTLINE, saw type
NRF24E2 uses the QFN 36LD 6x6 Saw type package., with SnPb plating. Dimensions are in mm.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Package Type
QFN36 (6x6 mm) Min typ. Max
A
0.8 1
A1
0.0 0.05
A2
0.75 1
b
0.2 0.25 0.3
D
E
e
J
4.47 4.57 4.67
K
4.47 4.57 4.67
L
0.35 0.4 0.45
6 BSC
6 BSC
0.5 BSC
Figure 12-2 : NRF24E2 package outline.
13 ABSOLUTE MAXIMUM RATINGS L
Supply voltages VDD ............................ - 0.3V to + 3.6V VSS ...................................................0V Input voltage For analog pins, AIN0 to AIN7 and AREF : VIA ................................. - 0.3V to 2.0 V For all other pins : VI ........................- 0.3V to VDD + 0.3V Output voltage VO .......................- 0.3V to VDD + 0.3V Total Power Dissipation PD (TA=85C)...............................60mW Temperatures Operating Temperature.... - 40C to + 85C Storage Temperature....... - 40C to + 125C Note: Stress exceeding one or more of the limiting values may cause permanent damage to the device. 13.1.1 ATTENTION!
Electrostatic Sensitive Device Observe Precaution for handling.
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PRODUCT SPECIFICATION
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14 Peripheral RF Information
14.1.1 Antenna output The ANT1 & ANT2 output pins provide a balanced RF output to the antenna. The pins must have a DC path to VDD, either via a RF choke or via the center point in a dipole antenna. The load impedance seen between the ANT1/ANT2 outputs should be in the range 200-700. A load of 100+j175 is recommended for maximum output power (0dBm). Lower load impedance (for instance 50 ) can be obtained by fitting a simple matching network.
14.1.2 Output Power adjustment
Power setting bits of configuring word RF output power DC current consumption
11 0 dBm 3dB 16.0 mA 10 -5 dBm 3dB 13.5 mA 01 -10 dBm 3dB 12.4 mA 00 -20 dBm 3dB 11.8 mA Conditions: VDD = 3.0V, VSS = 0V, T A = 27C, Load impedance = 100+j175.
Table 14-1 RF output power setting for the NRF24E2. 14.1.3 Crystal Specification Tolerance includes initially accuracy and tolerance over temperature and aging.
Frequency
4 MHz 8 MHz 12 MHz 16 MHz 20 MHz
CL
12pF 12pF 12pF 12pF 12pF
ESR
150 100 100 100 100
C0max
7.0pF 7.0pF 7.0pF 7.0pF 7.0pF
Tolerance
30ppm 30ppm 30ppm 30ppm 30ppm
Table 14-2 Crystal specification of the NRF24E2. To achieve a crystal oscillator solution with low power consumption and fast start-up time, it is recommended to specify the crystal with a low value of crystal load capacitance. Specifying CL=12pF is OK, but it is possible to use up to 16pF. Specifying a lower value of crystal parallel equivalent capacitance, C0 will also work, but this can increase the price of the crystal itself. Typically C0=1.5pF at a crystal specified for C0_max=7.0pF. The selected frequency value must also be set into the nRF2401 configuration word, please see Table 4-9 Crystal frequency setting.
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14.2 PCB layout and de-coupling guidelines
A well-designed PCB is necessary to achieve good RF performance. Keep in mind that a poor layout may lead to loss of performance, or even functionality, if due care is not taken. A fully qualified RF-layout for the NRF24E2 and its surrounding components, including matching networks, can be downloaded from www.nordicsemi.no. A PCB with a minimum of two layers including a ground plane is recommended for optimum performance. The NRF24E2 DC supply voltage should be de-coupled as close as possible to the VDD pins with high performance RF capacitors, see Table 15-1. It is preferable to mount a large surface mount capacitor (e.g. 4.7F tantalum) in parallel with the smaller value capacitors. The NRF24E2 supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the NRF24E2 IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. One via hole should be used for each VSS pin. Full swing digital data or control signals should not be routed close to the crystal or the power supply lines.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
15 Application example 15.1 NRF24E2 with single ended matching network
xxx
R5 AREF 1k AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 C14 1nF C15 100nF
VDD C5 1nF C6 10nF 36 35 34 33 32 31 30 29 28
R2 22k
P1.2 AIN1 AIN2 VSS VDD VSS AIN3 AIN4 AREF
VDD IREF AIN5 AIN6 AIN7 VSS VDD VSS_PA ANT2 ANT1 27 26 25 24 23 22 21 20 19 L 4 C10 1.0pF L 1 3.3nH L 2 10nH U1 NRF24E2 C9 1.0pF 5.6nH C11 L 3 5.6nH 2.2pF C12 RF I/O 4.7pF
xxx
DIN1 DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 VDD R3 10k U2 1 2 3 4 R4 10k CS SO WP VSS 25XX320 VCC HOLD SCK SI 8 7 6 5 VDD
10 11 12 13 14 15 16 17 18
P0.4 P0.5 P0.6 P0.7 DVDD VSS XC2 XC1 VDD_PA
1 2 3 4 5 6 7 8 9
VDD AIN0 DVDD2 P1.0 P1.1 P0.0 P0.1 P0.2 P0.3
NRF24E2
xxx
X1
C3 4.7pF
C4 2.2nF
C13 10nF
C7 1nF
C8 33nF R1
16 MHz 1M C1 22pF
C2 22pF
xxx
Figure 15-1 NRF24E2 schematic for RF layout with single end 50 antenna
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NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Component
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 L1 L2 L3 L4 R1 R2 R3 R4 R5 U1 X1 U2
Description
Capacitor ceramic, 50V, NPO Capacitor ceramic, 50V, NPO Capacitor ceramic, 50V, NPO Capacitor ceramic, 50V, X7R Capacitor ceramic, 50V, X7R Capacitor ceramic, 50V, X7R Capacitor ceramic, 50V, X7R Capacitor ceramic, 50V, X7R Capacitor ceramic, 50V, NPO Capacitor ceramic, 50V, NPO Capacitor ceramic, 50V, NPO Capacitor ceramic, 50V, NPO Capacitor ceramic, 50V, X7R Capacitor ceramic, 50V, X7R Capacitor ceramic, 50V, X7R Inductor, wire wound 2) Inductor, wire wound 2) Inductor, wire wound 2) Inductor, wire wound 2) Resistor Resistor Resistor Resistor Resistor NRF24E2 transmitter Crystal, CL = 12pF, ESR < 100 ohm 4 kbyte serial EEPROM with SPI interface
Size
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 QFN36 / 6x6 LxWxH = 4.0x2.5x0.8 SO8
Value
22 22 4.7 2.2 1.0 10 1 33 1.0 1.0 2.2 4.7 10 1.0 100 3.3 10 5.6 5.6 1.0 22 10 10 1 NRF24E2 161) 2XX320
Tolerance
5% 5% 5% 10% 10% 10% 10% 10% 0.1 pF 0.1 pF 0.25 pF 0.25 pF 10% 10% 10% 5% 5% 5% 5% 5% 1% 5% 5% 5% +/- 30 ppm
Units
pF pF pF nF nF nF nF nF pF pF pF pF nF nF nF nH nH nH nH M k k k k MHz
Table 15-1 Recommended components (BOM) in NRF24E2 with antenna matching network
2)
Wire wound inductors are recommended, other can be used if their self-resonant frequency (SRF) is > 2.7 GHz 1) NRF24E2 can operate at several crystal frequencies, please refer to 98.
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PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
15.2 PCB layout example
Figure 15-2 shows a PCB layout example for the application schematic in Figure 15-1. A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane.
No components in bottom layer Top silk screen
Top view Bottom view Figure 15-2 NRF24E2 RF layout with single ended connection to 50 antenna and 0603 size passive components
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 102 of 109 June 2004
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
16 Table of Figures
Figure 1-1 NRF24E2 block diagram plus external components ..........................................5 Figure 3-1 : SPI interface timing......................................................................................19 Figure 4-1 : Transmitter interface....................................................................................21 Figure 4-2Clocking in data with CPU and sending with ShockBurstTM technology............23 Figure 4-3 RF Current consumption with & without ShockBurstTM technology.................23 Figure 4-4 Flow Chart ShockBurstTM Transmit of transmitter subsystem.........................24 Figure 4-5Data packet set-up.........................................................................................26 Figure 4-6 Data Package Diagram..................................................................................31 Figure 4-7 Timing diagram for power down (or VDD off) to configuration mode for transmitter subsystem...............................................................................................33 Figure 4-8 Power down (or VDD off) to active mode.....................................................34 Figure 4-9 Timing diagram for configuration of transmitter subsystem...............................34 Figure 4-10 Timing of ShockBurstTM in TX ....................................................................36 Figure 5-1 : Block diagram of A/D converter..................................................................38 Figure 5-2 Typical use of A/D with 2 ratiometric inputs...................................................41 Figure 5-3 : Timing diagram single step conversion. .........................................................42 Figure 5-4 : Timing diagram continuous mode conversion. ...............................................43 Figure 8-18-2 : RTC and watchdog block diagram.........................................................53 Figure 10-1 : Memory Map and Organization.................................................................58 Figure 10-2 : Timer 0/1 - Modes 0 and 1.......................................................................76 Figure 10-3 : Timer 0/1 - Mode 2..................................................................................77 Figure 10-4 : Timer 0 - Mode 3.....................................................................................77 Figure 10-5 : Timer 2 - Timer/Counter with Capture.......................................................80 Figure 10-6 : Timer 2 - Timer/Counter with Auto-Reload...............................................81 Figure 10-7 : Timer 2 - Baud Rate Generator Mode.......................................................82 Figure 10-8 : Serial Port Mode 0 receive timing for low-speed (CPU_clk/12) operation..84 Figure 10-9 : Serial Port Mode 0 receive timing for high-speed (CPU_clk/4) operation...84 Figure 10-10 : Serial Port Mode 0 transmit timing for high-speed (CPU_clk/4)................84 Figure 10-11 : Serial Port Mode 0 transmit timing for high-speed (CPU_clk/4)................84 Figure 10-12 : Serial port Mode 1 Transmit Timing.........................................................87 Figure 10-13 : Serial port Mode 1 Receive Timing..........................................................87 Figure 10-14 : Serial port Mode 2 Transmit Timing.........................................................89 Figure 10-15 : Serial port Mode 2 Receive Timing..........................................................89 Figure 10-16 : Serial port Mode 3 Transmit Timing.........................................................90 Figure 10-17 : Serial port Mode 3 Receive Timing..........................................................91 Figure 12-1 : NRF24E2G GREEN Package outline.........................................................95 Figure 12-2 : NRF24E2 package outline..........................................................................96 Figure 15-1 NRF24E2 schematic for RF layout with single end 50 antenna .................100 Figure 15-2 NRF24E2 RF layout with single ended connection to 50 antenna and 0603 size passive components........................................................................................102
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 103 of 109 June 2004
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
17 Table of Tables
Table 1-1 : NRF24E2 quick reference data .......................................................................4 Table 1-2 : NRF24E2 ordering information........................................................................4 Table 1-3 : NRF24E2 pin function.....................................................................................7 Table 2-1 : SFR Register map........................................................................................11 Table 3-1 : Port functions ...............................................................................................14 Table 3-2 : Port 0 (P0) functions ....................................................................................15 Table 3-3 : Port 0 control and data SFR-registers...........................................................15 Table 3-4 : Port 1 (P1) functions ....................................................................................16 Table 3-5 : Port 1 control and data SFR-registers...........................................................17 Table 3-6 : SPI control and data SFR-registers...............................................................18 Table 4-1 : nRF2401 2.4GHz transmitter subsystem control registers - SFR 0xA0 and 0xB3.......................................................................................................................20 Table 4-2 : RADIO register - SFR 0xA0, default initial data value is 0x80.......................20 Table 4-3 : Transmitter SPI interface. .............................................................................21 Table 4-4 transmitter subsystem main modes ..................................................................22 Table 4-5 Table of configuration words. .........................................................................27 Table 4-6 Configuration data word.................................................................................28 Table 4-7 CRC setting. ..................................................................................................29 Table 4-8 RF operational settings...................................................................................29 Table 4-9 Crystal frequency setting.................................................................................30 Table 4-10 RF output power setting. ..............................................................................30 Table 4-11 Frequency channel setting.............................................................................30 Table 4-12 Data package description.............................................................................31 Table 4-13 Operational timing for transmitter subsystem..................................................33 Table 5-1 : ADCCON register, SFR 0xA1, default initial data value is 0x80....................39 Table 5-2 : ADCSTATIC register, SFR 0xA4, default initial data value is 0x0A. .............39 Table 5-3 : ADC data SFR-registers, SFR 0xA2 and 0xA3............................................39 Table 6-1 : PWM control registers - SFR 0xA9 and 0xAA.............................................44 Table 7-1 : NRF24E2 interrupt sources ...........................................................................45 Table 7-2 : IE Register - SFR 0xA8...............................................................................46 Table 7-3 : IP Register - SFR 0xB8...............................................................................46 Table 7-4 : EXIF Register - SFR 0x91 ..........................................................................47 Table 7-5 : EICON Register - SFR 0xD8 ......................................................................47 Table 7-6 : EIE Register - SFR 0xE8.............................................................................47 Table 7-7 : EIP Register - SFR 0xF8.............................................................................48 Table 7-8 : Interrupt Natural Vectors and Priorities.........................................................49 Table 7-9 : Interrupt Flags, Enables, and Priority Control................................................49 Table 8-1 : TICK control register - SFR 0xB5 ...............................................................51 Table 8-2 : RTC and Watchdog SFR-registers ...............................................................54 Table 8-3 Reset control registe - SFR 0xB1. ..................................................................55 Table 9-1 : PCON Register - SFR 0x87........................................................................55 Table 9-2 : CK_CTRL register - SFR 0xB6..................................................................56 Table 9-3 : Startup times from Power down mode..........................................................57
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 104 of 109 June 2004
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
Table 10-1 : EEPROM layout ........................................................................................59 Table 10-2 : Legend for Instruction Set Table .................................................................60 Table 10-3 : NRF24E2 Instruction Set, Arithmetic Instructions.........................................62 Table 10-4 : NRF24E2 Instruction Set, Logical Instructions.............................................63 Table 10-5 : NRF24E2 Instruction Set, Boolean Instructions............................................64 Table 10-6 : NRF24E2 Instruction Set, Data Transfer Instructions. ..................................65 Table 10-7 : NRF24E2 Instruction Set, Branching Instructions.........................................66 Table 10-8 : NRF24E2 Instruction Set, Miscellaneous Instructions...................................67 Table 10-9 : Special Function Registers summary...........................................................70 Table 10-10 : Special Function Register reset values and description, alphabetically. .......72 Table 10-11 : PSW Register - SFR 0xD0......................................................................72 Table 10-12 : SFR registers unique to NRF24E2.............................................................73 Table 10-13 : TMOD Register - SFR 0x89 ...................................................................75 Table 10-14 : TCON Register - SFR 0x88....................................................................75 Table 10-15 : CKCON Register - SFR 0x8E, ...............................................................78 Table 10-16 : T2CON Register - SFR 0xC8 .................................................................80 Table 10-17 : Timer 2 Mode Control Summary..............................................................80 Table 10-18 : Serial Port Modes ....................................................................................82 Table 10-19 : SCON Register - SFR 0x98....................................................................83 Table 10-20 : Timer 1 Reload Values for Serial Port Mode 1 Baud Rates .......................85 Table 10-21 : Timer 2 Reload Values for Serial Port Mode 1 Baud Rates.......................86 Table 11-1 : NRF24E2 Electrical specifications ...............................................................93 Table 14-1 RF output power setting for the NRF24E2.....................................................98 Table 14-2 Crystal specification of the NRF24E2............................................................98 Table 15-1 Recommended components (BOM) in NRF24E2 with antenna matching network ................................................................................................................101 Table 18-1 :Definitions .................................................................................................106
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 105 of 109 June 2004
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
18 DEFINITIONS
Data sheet status
Objective product specification Preliminary product specification Product specification This datasheet contains target specifications for product development. This datasheet contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later. This datasheet contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Table 18-1 :Definitions Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor does not assume any liability arising out of the application or use of any product or circuits described herein.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale.
Product Specification: Revision Date: 10.06.2004. Datasheet order code: 100604-NRF24E2.
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 106 of 109 June 2004
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
All rights reserved (R). Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 107 of 109 June 2004
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
YOUR NOTES
Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 108 of 109 June 2004
PRODUCT SPECIFICATION
NRF24E2 2.4 GHz Radio Transmitter with Microcontroller
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Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Revision: 1.2 Page 109 of 109 June 2004

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